IA-64 Architecture

The architecture that Intel suggests to execute those instructions, that was called Merced (used on the Itanium processor), is versatile and promises performance by means of the simultaneous (parallel) execution of up to 6 instructions. Figure 2 shows the diagram in blocks of this architecture that uses a pipeline of 10 stages.

Intel 64-bit architecture (IA-64)Figure 2: Block diagram of the Itanium CPU (IA-64 architecture).

The IA-64 architecture receives the sigla EPIC, which means Explicit Parallel Instruction Computing. By using this sigla, Intel wants to say that the compiler will be the great responsible for determining and clearing the parallelism present in the instructions to be executed. This is a combination of concepts called speculation, predication and explicit parallelism. Next, we will briefly study each one of them.

The Instruction Level Parallelism – ILP is the ability of executing multiple instructions at the same time. As we have seen, the IA-64 architecture allows to pack independent instructions to be executed in parallel and, for each clock period, is capable of treating multiple packs. Due to the great number of features in parallel, as well as the great number of registers and multiple executing units, it is possible for the compiler to manage and program the parallel computing. The compilers used for the traditional architectures are limited in their speculative capacity because there is not always a way to be sure if the speculation will be correctly managed by the processor. The IA-64 architecture allows the compiler to explore the speculative information without sacrificing the correct execution of an application.

The IA-64 architecture has mechanisms denominated instruction pointer, suggestions for branches and cache, that allow the compiler to send to the processor information obtained during the time of compilation. That information minimizes the penalties that come from the branches and cache misses.

There are two kinds of speculation: data and control. With the speculation, the compiler advances an operation in a way that its latency (time spent) is removed from the critical way. The speculation is a form of allowing the compiler to avoid that slow operations spoil the parallelism of the instructions. Control speculation is the execution of an operation before the branch that precedes it. On the other hand, data speculation is the execution of a memory load before a storage operation (store) that precedes it and with which it can be related.

With the predication you mark with predicates all the branches of the conditional branches that, next, are sent to the execution in parallel, however only the necessary ones are executed. Therefore, it is possible to prepare the execution of the instructions even before having solved the conditional branches. Besides the removal of branches by means of predicates, IA-64 architecture has a series of mechanisms that should reduce the error in predicting the branches and the cost when this error happens.

The IA-64 architecture has a great number of registers. There are 128 integer registers, 128 floating-point registers, 64 predicate registers of 1 bit, and many other registers for configuration, management and monitoring of the CPU’s performance.


Ricardo Zelenovsky, PhD, is professor at UNB (Universidade de Brasília), a Brazilian Engineering University. Together with Alexandre Mendonça, Zelenovsky wrote several books about computer hardware. Visit their website at