Independent Memory Controller

The higher the data the CPU fetches from the RAM memory per clock cycle the faster the system will be. As we explained on the previous page, the CPU is a lot faster than the RAM memory, so the less times it needs to fetch data from the memory the better. Loading lots of data at once prevents this from happening.

Memory modules are 64-bit devices. Instead of launching 128-bit memory modules, CPU and chipset manufacturers came with the idea of dual-channel memory, a way to access two memory modules simultaneously, as if these two 64-bit memory modules were a single 128-bit module. This doubles the memory access transfer rate, as now instead of one 64-bit data two 64-bit data can be loaded per clock cycle.

The problem with dual-channel technology is that the second 64-bit data that is loaded together with the data that was originally requested is necessarily stored on the following address. For example, if the CPU asked for the data A stored in address 1, the memory controller will automatically load data A and data B, which is stored in address 2.

If the CPU doesn’t have a use for this data B, this second load will be completely wasted, as the memory controller cannot use this parallel loading to read a data that is stored on an address that is not the following address.

The memory controller used on K10 architecture allows the CPU to load a data stored on an address different from the next address. This independency will increase the CPU performance by not wasting memory loads. Figure 5 illustrates this feature, where the CPU wanted to load data A and F. On K8 architecture, illustrated on the left side, two data fetches are needed (as two data are completely useless), while on K10 architecture only one data fetch is needed.

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Figure 5: Independent memory controller.

Informally the independent architecture used on K10 is called "un-ganged", while the previous implementation that is used nowadays is called "ganged".

AMD calls this feature as “AMD Memory Optimizer Technology”.

By the way, it seems that AMD fixed the “broken divider” problem found on current socket AM2 CPUs. Let’s wait to see if that is really true.

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