CAS Latency (CL)

As mentioned before, CAS Latency (CL) is the most famous memory parameter. It tells us how many clock cycles the memory will delay to return a requested data. A memory with CL = 3 will delay three clock cycles to deliver data, while a memory with CL = 5 will delay five clock cycles to perform the same operation. Thus two memory modules running at the same clock rate the one with the lowest CL will be the faster.

Notice that the clock rate here is the real clock rate under which the memory module is running – i.e. half the rated clock rate. As DDR and DDR2 memories can deliver two data per clock cycle, they are rated with the double of their real clock rate.

On Figure 4 you can see how CL works. We gave two examples, a memory module with CL = 3 and a memory module with CL = 5. The command in blue would be a “read” command.

click to enlarge
Figure 4: CAS Latency (CL).

A memory with CL = 3 will provide a 40% improvement on memory latency over a memory with CL = 5, considering both running at the same clock rate.

You can even calculate the time the memory delays until it starts delivering data. The period of each clock cycle can be easily calculated thru the formula:

T = 1 / f

Thus the period of each clock cycle of a DDR2-533 memory running at 533 MHz (266.66 MHz clock) would be 3.75 ns (ns = nanosecond; 1 ns = 0.000000001 s). Keep in mind that you need to use the real clock rate, which is half the labeled clock rate. So this DDR2-533 memory would delay 18.75 ns to start delivering data, if it had CL =5, or 11.25 ns, if it had CL =3, for example.

SDRAM, DDR and DDR2 memories implement burst mode, where data after the first requested data delays only one clock cycle to exit the memory, if the next requested data is located in the address right after the current requested address. So, while the first data would delay CL clock cycles to exit the memory, the next data would be delivered right after the data that has just came out from the memory, not having to wait another CL cycle.

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