HyperTransport 1.x

HyperTransport bus can operate under several different clock and width (i.e. number of bits that are transmitted per time) configurations. This is probably where there are a lot of misconceptions and mistakes regarding HyperTransport are said and written.

HyperTransport is a bus created by a consortium made of several companies, including AMD, nVidia and Apple. This bus can be used on several applications and it is not limited to AMD processors.

This means that the actual configuration of the HyperTransport bus will depend on the hardware developer.

Also some developers announce an exaggerated transfer rate of the HyperTransport bus they are using.

Current AMD64 processors use HyperTransport 1 (HT1) or HyperTransport 2 (HT2), with forthcoming AMD processors using HyperTransport 3 (HT3). In all these cases, AMD processors use 16-bit links, even though HyperTransport allows the use of 32-bit links.

HyperTransport 1 is used on all socket 754 processors and socket AM2 Sempron processors (other AM2-based processors use HyperTransport 2.0).

Here is a breakdown of all possible clock and transfer rates on HyperTransport 1.x (i.e. available on socket 754 processors):

• 200 MHz = 400 MT/s = 800 MB/s
• 400 MHz = 800 MT/s = 1,600 MB/s
• 600 MHz = 1,200 MT/s = 2,400 MB/s
• 800 MHz = 1,600 MT/s = 3,200 MB/s

HyperTransport transfers two data per clock cycle, a concept also known as DDR, double data rate.

The formula to find the maximum theoretical transfer rate is:

Transfer rate = width (number of bits) x clock x number of data per clock cycle / 8

Thus with socket 754 processors, HyperTransport bus can work up to 800 MHz or 3,200 MB/s. Some people advertise this clock and transfer rate using other numbers, generating a lot of confusion on the market:

• Some say that the clock rate used by HyperTransport 1.x is of 1,600 MHz. This happens because since on each clock cycle two data are transferred, the performance obtained is similar to 1,600 MHz clock rate transferring only one data per clock cycle. At the end the transfer rate will be the same, as on the above formula instead of using “2” for “number of data per clock cycle”, it will be used “1” instead. This is the same thing that happens with DDR and later memories, where the announced clock rate is double the actual clock rate (e.g. DDR2-800 memories work in fact at 400 MHz transferring two data per clock cycle).
• AMD says that the clock rate is of 1,600 MT/s. MT/s stands for Mega Transfers per Second, or millions of transfers per second. This is the correct way to express the above idea. Transfers per second are equal to the clock rate times the number of data transferred per clock cycle.
• Some say that the maximum transfer rate of HyperTransport 1.x is 6,400 MB/s. This happens because the announced transfer rate is for each datapath (i.e. 3,200 MB/s for the input datapath and 3,200 MB/s for the output datapath), so some people simple multiply the transfer rate by two to cover the two datapaths. We don’t agree with this methodology. In brief, it is as if we said that a highway has a speed limit of 130 MPH just because there is a speed limit of 65 MPH in each direction. Makes no sense.

Another misunderstanding is saying that the external bus or FSB (Front Side Bus) of Athlon 64 (or any other AMD64-based CPU) is of 1,600 MHz. This is partially right. We can say this regarding I/O operations but not for memory, as processors based on AMD64 architecture have two separated external busses, as we saw. Thus it is better if you say HyperTransport and not “external bus” nor “FSB” to not create confusion.

It is important to notice that AMD processors can work with several other clock rates below the announced 1,600 MT/s (800 MHz). In fact they can work with any of the speeds on the list published above.

The chipset can negotiate a lower clock rate with the CPU and even an 8-bit width instead of the 16-bit one. In fact when the first Athlon 64 chipsets came out VIA claimed that their chipset for the Athlon 64, the K8T800, was superior to the competition for working with the HyperTransport bus at 1,600 MT/s accusing the competition (without mentioning names) of not working at the maximum transference rate the HyperTransport permits, but rather at one of those inferior taxes or even using 8-bit transfers instead of 16-bit ones.

At http://www.hypertransport.org, HyperTransport’s official website, you will see that they announce a maximum transfer rate of 12.8 GB/s for HyperTransport 1.x. This maximum transfer rate is achieved by using 32-bit links – as we explained AMD processors use 16-bit links. But if you do the math you will find 6,400 MB/s (32 bits x 800 MHz x 2 / 8). Here the consortium doubled the maximum transfer rate just because there are two datapaths available (one for transmitting and another for receiving). As we said before, we do not agree with this methodology of calculating transfer rates.

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