Intel has decided to brand both its upcoming desktop (Conroe) and notebook (Merom) chips as Core 2 Duo. The dual-core processors will also be identified by sequence numbers: E4X00 or E6X00 for the desktop parts and T5X00 or T7X00 for the mobile ones. Intel will rename its high-performance version of Conroe as Core 2 Extreme. The server-aimed Woodcrest, the first next-generation product to arrive, in June, will likely keep the Xeon brand.
Intel has quietly started shipping the anticipated Pentium D 960 processor. The new top-of-the-line dual-core model is clocked at 3.6 GHz, uses 800 MHz FSB and packs 4 MB of L2 cache (2 MB per core). It supports EM64T, Virtualization Technology (VT), Enhanced SpeedStep and Execute Disable. The part costs USD 637 in 1,000-unit quantities.
Intel today introduced its new platform brand aimed at business desktops. With the vPro concept, based on upcoming Core processors and Broadwater chipsets, the company promises remote manageability, improved security and energy efficiency. The platform will sport the second-generation of Intel’s Active Management Technology (AMT) and Virtualization Technology (VT). It is planned to debut in the second quarter.
As expected, Intel this week formally launched two ultra low voltage Core Solo processors, the U1300, clocked at 1.06 GHz, and the U1400, running at 1.2 GHz. Power consumption in both products is limited to 5.5 W. The single-core 65-nm chips sport 533 MHz frontside bus and 2 MB of L2 cache. Gateway and Fujitsu had already announced ultraportable notebooks based on the processors.
Azul Systems has announced that the next generation of its Vega processor will feature 48 cores. Produced by Taiwan Semiconductor Manufacturing Company (TSMC) in a 90-nm process, the 64-bit Vega 2 consists of 812 million transistors. It is designed to power network-attached systems with up to 768 cores, supporting 768 GB of memory, aimed at accelerating Java and other virtual-machines. Such equipment is expected to be available in 2007.
AMD will hold a public demonstration of its virtualization technology, code-named Pacifica, at LinuxWorld, set to take place April 3-6 in Boston. The display will be made on Opteron-based machines. Virtualization enables a single processor to act as if it were several CPUs and, thus, run multiple operating systems simultaneously. Intel already sells some chips featuring the technology.
VIA has just launched their latest CPU model, C7-M ULV (Ultra Low Voltage). Available in versions from 1 GHz to 1.5 GHz with power dissipation between 3.5 W and 7.5 W and measuring only 0.83” x 0.83” (21 mm x 21 mm), it is a great product for small PCs for embedded applications and consumer electronics devices. It features the same features as C7-M, which we have already explained in our article about it.
Intel has just unveiled details of the new microarchitecture that will be used by the new CPU generations to be released this year, including Merom, Conroe and Woodcrest. Called "Core", this new microarchitecture is based on Pentium M's (which is based on Pentium III's). Enhancements include macro-fusion, which consists in packing two x86 instructions into just one to be processed together, advanced pre-fetch, advanced power gating and a shared L2 memory cache (i.e. the two CPU cores will have access to a single cache, instead of having one dedicated cache per core).
We will be publishing a detailed tutorial on this new architecture pretty soon.
The Inquirer reports that AMD will release an Opteron processor clocked at 3 GHz in the beginning of the second quarter. The 90-nanometer single-core 256, aimed at two-way servers, should have 1 MB of L2 cache and use socket 940, like previous models. Sources told the Web site that it will be “competitively” priced.
AMD has announced the broad availability of its Pacifica virtualization technology specification under a royalty-free license. It is expected to be supported by all the company’s processors starting in mid-2006. The virtualization tech complements software-based approaches in managing, partitioning and securing I/O devices. AMD is working closely with leading developers Microsoft, VMware and XenSource.
A group of nine companies has pledged USD 10 billion to increase adoption of the Itanium processor until 2010. The money will be spent in research, marketing and partnerships. All contributors (Intel and HP, co-developers of the chip, as well as Bull, Fujitsu, Fujitsu Siemens, Hitachi, NEC, SGI and Unisys) are members of the Itanium Solutions Alliance. New Montecito Itaniums sporting 18 MB of L2 cache are expected to be launched in the middle of this year.
AMD plans to demo its quad-core server chips, expected to be commercialy available in 2007, in the middle of this year. The company’s goal is to show compatibility with its upcoming socket F platform, which will be used by new dual-core models supporting DDR2 and virtualization technologies, among other features. Marty Seyer, an AMD vice president, told InformationWeek that solution providers will need only to flash the bios to run quad-core chips on socket F motherboards.
Intel today claimed to be the first company to produce a fully functional SRAM chip using 45-nanometer technology. The feat is supposed to prove it is on schedule to offer 45-nm processors in the second half of 2007. The 153 Mb SRAM chip, manufactured in Intel’s D1D facility in Oregon, contain more than 1 billion transistors. The company has already begun construction of two new 45-nm fabs in Arizona and Israel.
The Register reports that Intel has begun shipping two low-cost single-core Pentium 4s. The 517 and 524 models are clocked at 2.93 GHz and 3.06 GHz, feature 533 MHz FSB and contain 1 MB of L2 cache. Hyper-Threading is supported. Furthermore, Intel will start selling a budget dual-core chip, the long-awaited Pentium D 805, in March. The processor runs at 2.66 GHz, uses 533 MHz FSB and is equipped with 1 MB of L2 cache per core.
AMD has signed a deal with Innovative Silicon to license a cache technology that is said to achieve five times the density of embedded SRAM and twice that of embedded DRAM. With Z-RAM (Zero Capacitor RAM) cache sizes could reach 5 MB without increasing the die. Z-RAM requires silicon-on-insulator (SOI) process, the same used by AMD to make its processors. The company will test the tech for compatibility, but did not disclose specific timetables.
