Sandy Bridge is the name of the new microarchitecture Intel CPUs will be using starting in 2011. It is an evolution of the Nehalem microarchitecture that was first introduced in the Core i7 and also used in the Core i3 and Core i5 processors.
If you don’t follow the CPU market that closely, let’s make a quick recap. After the Pentium 4, which was based on Intel’s 7th generation microarchitecture, called Netburst, Intel decided to go back to their 6th generation microarchitecture (the same one used by Pentium Pro, Pentium II, and Pentium III, dubbed P6), which proved to be more efficient. From the Pentium M CPU (which is a 6th generation Intel CPU), Intel developed the Core architecture, which was used on the Core 2 processor series (Core 2 Duo, Core 2 Quad, etc). Then, Intel got this architecture, tweaked it a little bit more (the main innovation was the addition of an integrated memory controller), and released the Nehalem microarchitecture, which was used on the Core i3, Core i5, and Core i7 processor series. And, from this microarchitecture, Intel developed the Sandy Bridge microarchitecture, which will be used by the new generation of Core i3, Core i5, and Core i7 processors to be released in 2011 and 2012.
For better understanding the present tutorial, we recommend you to read the following tutorials, in this particular order:
- Inside Pentium M Architecture
- Inside Intel Core Microarchitecture
- Inside Intel Nehalem Microarchitecture
The main specifications for the Sandy Bridge microarchitecture are summarized below. We will explain them in more detail in the next pages.
- The north bridge (memory controller, graphics controller and PCI Express controller) is integrated in the same chip as the rest of the CPU. In Nehalem-based CPUs, the north bridge is located in a separate silicon chip packed together with the CPU silicon chip. In fact, with 32-nm Nehalem-based CPUs the north bridge is manufactured under 45-nm process.
- First models will use a 32-nm manufacturing process
- Ring architecture
- New decoded microinstructions cache (L0 cache, capable of storing 1,536 microinstructions, which translates in more or less to 6 kB)
- 32 kB L1 instruction and 32 kB L1 data cache per CPU core (no change from Nehalem)
- L2 memory cache was renamed to “mid-level cache” (MLC) with 256 kB per CPU core
- L3 memory cache is now called LLC (Last Level Cache), it is not unified anymore, and is shared by the CPU cores and the graphics engine
- Next generation Turbo Boost technology
- New AVX (Advanced Vector Extensions) instruction set
- Improved graphics controller
- Redesigned DDR3 dual-channel memory controller supporting memories up to DDR3-1333
- Integrated PCI Express controller supporting one x16 lane or two x8 lanes (no change from Nehalem)
- First models will use a new socket with 1155 pins
- 1. Introduction
- 2. Enhancements to the CPU Pipeline
- 3. The AVX Instruction Set
- 4. The Ring Architecture
- 5. Next Generation Turbo Boost
- 6. The Integrated Graphics Engine