Inside the Intel Haswell Microarchitecture

New Instructions

The AVX2 instruction set expands the existing AVX instruction set to allow the use of 256-bit registers with integer operations. With the AVX instruction set, integer operations are limited to 128-bit registers, and 256-bit registers are only used with floating-point operations.

In addition, the AVX2 instruction supports three-operand Fused Multiply-Add (FMA) instructions (a.k.a. FMA3), which are able to execute operations such as a x b + c with a single instruction. These instructions were already supported by AMD CPUs based on the Piledriver microarchitecture. Two FMA execution units were added to the microarchitecture, as we will show on the next page.

New 15 bit manipulation instructions (BMI) were added. These instructions, which are listed in Figure 1, may be used for cryptography, indexing, and data conversion.

HaswellFigure 1: New bit manipulation instructions

The third new instruction set added to the Haswell microarchitecture is called TSX or Transactional Synchronization eXtensions, and is used to help solve data synchronization issues when the same data may be used by different processes that are running at the same time.

All new instruction sets are described in detail in the “Intel Architecture Instruction Set Extensions Programming Reference.” (The file downloads without an extension; it is a PDF file.)

To use any of those new instruction sets, the program you are running must support them, of course.

Author: Gabriel Torres

Gabriel Torres is a Brazilian best-selling ICT expert, with 24 books published. He started his online career in 1996, when he launched Clube do Hardware, which is one of the oldest and largest websites about technology in Brazil. He created Hardware Secrets in 1999 to expand his knowledge outside his home country.

Share This Post On
Subscribe To Our Newsletter

Subscribe To Our Newsletter

Join our mailing list to receive the latest news and updates from our website.

You have been added to our newsletter!