The AVX2 instruction set expands the existing AVX instruction set to allow the use of 256-bit registers with integer operations. With the AVX instruction set, integer operations are limited to 128-bit registers, and 256-bit registers are only used with floating-point operations.
In addition, the AVX2 instruction supports three-operand Fused Multiply-Add (FMA) instructions (a.k.a. FMA3), which are able to execute operations such as a x b + c with a single instruction. These instructions were already supported by AMD CPUs based on the Piledriver microarchitecture. Two FMA execution units were added to the microarchitecture, as we will show on the next page.
New 15 bit manipulation instructions (BMI) were added. These instructions, which are listed in Figure 1, may be used for cryptography, indexing, and data conversion.
The third new instruction set added to the Haswell microarchitecture is called TSX or Transactional Synchronization eXtensions, and is used to help solve data synchronization issues when the same data may be used by different processes that are running at the same time.
All new instruction sets are described in detail in the “Intel Architecture Instruction Set Extensions Programming Reference.” (The file downloads without an extension; it is a PDF file.)
To use any of those new instruction sets, the program you are running must support them, of course.
- 1. Introduction
- 2. New Instructions
- 3. New Dispatch Ports and Execution Units
- 4. New 2D Video Engine
- 5. New 3D Engine