The CPU Building Block
AMD decided to take a completely different approach in the new Bulldozer architecture. They decided to create a “dual-core” module that shares some resources (the front-end engine, the floating-point unit, and the L2 memory cache, see Figure 1) and, therefore, are not completely independent from each other.
According to AMD this was done in order to optimize the CPU and, at the same time, cut costs. The optimization comes from the fact that on a typical multi-core CPU several units inside the CPU remain idle, and these units could be combined in the Bulldozer architecture. And since the CPU will have less units, it can be smaller, which reduces the amount of material necessary to build the CPU, reducing costs. Having less units also help saving energy and reducing the amount of generated heat.
So while AMD will call a CPU that has one of these modules a “dual-core” CPU, in reality the CPU isn’t true a dual-core product, because there aren’t two complete and complete CPUs inside the product. The “dual-core” name in this case will be used for marketing purposes, to make sure the consumer understands that although this Bulldozer-based CPU isn’t a true “dual-core” model, it should perform like one.
Going further, for making a “quad-core” CPU, AMD will get two of these blocks and put together, so while physically speaking the processor has actually two “CPUs” inside (two of the building blocks shown in Figure 1), and not four, AMD will still call it a “quad-core” product. In Figure 2, you can see how an “eight-core” CPU based on the Bulldozer architecture would look like.
Let’s now take an in-depth look at the Fetch and Decode units used on the Bulldozer architecture.
- 1. Introduction
- 2. Instruction Sets
- 3. The CPU Building Block
- 4. The Fetch and Decode Units
- 5. The Execution Units
- 6. The L2 Memory Cache
- 7. Power Management