HyperTransport Bus and Multiprocessing

The communication between AMD64 CPUs and the bridge chip is made through a bus called HyperTransport. The HyperTransport speed depends on the CPU model. Typical values are of 3,200 MB/s (a.k.a. “800 MHz”, “1,600 MHz” or “6,400 MB/s”) or 4,000 MB/s (a.k.a. “1,000 MHz”, “2,000 MHz” or “8,000 MB/s”). For better understanding the HyperTransport bus, please read our tutorial on the subject.

AMD64 CPUs can have more than one HyperTransport bus. While all AMD64 CPUs targeted to desktops and notebooks – Athlon 64, Athlon 64 FX, Athlon 64 X2, Sempron and Turion 64 – have only one HyperTransport bus, AMD64 models for servers and workstations – Opteron – can have more than one HyperTransport bus.

Opteron CPUs from 1xx series don’t support multiprocessing and thus have only one HyperTransport bus and work just like shown in Figure 2. Opteron CPUs from 2xx series support multiprocessing up to two CPUs and have two HyperTransport busses. Opteron CPUs from 8xx series support multiprocessing up to eight CPUs and have three HyperTransport busses. These extra busses are used to interconnect the CPUs, see Figures 3 through 5.

Opteron 2xx MultiprocessingFigure 3: Opteron 2xx or 8xx series in dual-CPU multiprocessing configuration.

Opteron 4xx MultiprocessingFigure 4: Opteron 8xx in quad-CPU multiprocessing configuration.

AMD64 ArchitectureFigure 5: Opteron 8xx in eight-CPU multiprocessing configuration.

AMD approach to multiprocessing is also something very interesting to notice. Since each CPU has its own memory controller, each CPU accesses its own memory modules. For example, on a quad-Opteron system with 4 GB RAM, each CPU has 1 GB RAM for itself. On Xeon system, for example, the 4 GB would be shared by all CPUs. Also, since each CPU can drive up to four memory modules per channel, the quad-CPU system shown in Figure 4 could directly drive up to 32 memory modules (eight per CPU). The motherboard manufacturer, however, is who defines the number of sockets available on the motherboard (i.e., saying that a quad-Opteron system can have up to 32 memory modules does not translate into saying that all quad-Opteron systems have 32 memory sockets).

On the figures above you can see an “I/O” labeled. This “I/O” can represent any kind of bridge: it could be a regular south bridge; it could be an AGP or PCI Express x16 bridge for graphics; it could be a PCI-X or PCI Express for general purpose add-on cards, etc.

How the HyperTransport busses are connected inside the CPU is shown in Figure 6. AMD64 CPUs have a “crossbar”, which is in charge of routing data and commands from and to the CPU, memory and the HyperTransport busses. The System Request Interface (SRI) is also known as System Request Queue (SRQ), while APIC stands for Advanced Programmable Interrupt Controller. The diagram considers a dual-core CPU.

AMD64 ArchitectureFigure 6: How the HyperTransport busses are connected inside the CPU.

Gabriel Torres is a Brazilian best-selling ICT expert, with 24 books published. He started his online career in 1996, when he launched Clube do Hardware, which is one of the oldest and largest websites about technology in Brazil. He created Hardware Secrets in 1999 to expand his knowledge outside his home country.