Wait states are additional clock cycles inserted to the memory access cycle when the memory is slower than the CPU, in order to ”match“ the CPU speed and the memory speed.
For example, consider a classic Pentium processor, which has a 66 MHz external bus. Each external clock cycle has a 15 ns period (1/66 MHz). Each memory access cycle takes, at least two clock cycles or 30 ns. If we use 60 ns memories with this CPU, they won’t be able to ”talk“ to the CPU, since the CPU is faster than the memories (15 ns vs. 30 ns). So the PC won’t work.
The solution is to ”delay“ the CPU, inserting two extra clock cycles (i.e. two wait states) to the memory access cycle. These two extra clock cycles will turn the memory cycle to 60 ns (4 x 15 ns) ”matching“ the memory speed.
Even though wait states allow the CPU to ”talk“ to a slower RAM memory, this feature slows down the CPU performance. In the given example, the CPU will use four clock cycles to access RAM memory, but only two out of these four cycles are actually used to talk to the memory, the other two are there just to delay the CPU. In this example, the memory performance will be 50% below the CPU maximum transfer rate.