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Understanding RAM Timings
 Author: Gabriel Torres 1,647,762 views Type: Tutorials Last Updated: May 17, 2011 Page: 3 of 6 Select Page to Load Introduction Timings CAS Latency (CL) RAS to CAS Delay (tRCD) RAS Precharge (tRP) Other Parameters
CAS Latency (CL)
 As previously mentioned, CAS Latency (CL) is the best known memory parameter. It tells us how many clock cycles the memory will delay to return requested data. A memory with CL = 7 will delay seven clock cycles to deliver data, while a memory with CL = 9 will delay nine clock cycles to perform the same operation. Thus, for two memory modules running at the same clock rate, the one with the lowest CL will be faster.Notice that the clock rate here is the real clock rate under which the memory module is running – i.e., half the rated clock rate. As DDR, DDR2, and DDR3 memories can deliver two data per clock cycle, they are rated with double their real clock rate.In Figure 4, you can see how CL works. We gave two examples, a memory module with CL = 7 and a memory module with CL = 9. The command in blue would be a “read” command.click to enlargeFigure 4: CAS Latency (CL)A memory with CL = 7 will provide a 22.2% improvement on memory latency over a memory with CL = 9, considering that both are running at the same clock rate.You can even calculate the time the memory delays until it starts delivering data. The period of each clock cycle can be easily calculated through the formula:`T = 1 / f`Thus, the period of each clock cycle of a DDR3-1333 memory running at 1333 MHz (666.66 MHz clock) would be 1.5 ns (ns = nanosecond; 1 ns = 0.000000001 s). Keep in mind that you need to use the real clock rate, which is half of the labeled clock rate. So, this DDR3-1333 memory would delay 10.5 ns to start delivering data if it had CL =7, or 13.5 ns if it had CL = 9, for example.SDRAM, DDR, DDR2, and DDR3 memories implement burst mode, where data stored in the next addresses can exit the memory at only one clock cycle. So, while the first data would delay CL clock cycles to exit the memory, the next data would be delivered right after the prior data that has just come out from the memory, not having to wait for another CL cycle. Also, DDR, DDR2, and DDR3 memories deliver two data per clock cycle, and that is why they are labeled as having twice their real clock rate. Print Version | Send to Friend | Bookmark Article « Previous |  Page 3 of 6  | Next »

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