Since 1994, Intel and HP work at a 64-bit option. Its architecture should enable the CISC processors to take a big enough step to overtake the RISC processors. By using a technique called VLIW, still experimental at the time, and creating the EPIC model, they proposed the Merced architecture, which has been promised to the beginning of the year 2000. As things have changed, the processors Pentium III and IV and the Athlon have offered exceptional performance, reaching over 1 GHz, and because of this new architecture's high price and the low availability of programs to 64 bits, the timetable has been delayed and the release of the IA-64 architecture should happen only this year.

The letters VLIW mean Very Large Instruction Word. Processors that use this technique access the memory by transferring long program words, and in each word many instructions are packed. In the case of the IA-64, three instructions are used for each pack of 128 bits. As each instruction has 41 bits, there are 5 bits left that will be used to indicate the kinds of instruction that were packed. Figure 1 shows the instruction packaging scheme. This packaging lessens the number of memory accesses, leaving to the compiler the task of grouping the instructions in order to get the best of the architecture.

Figure 1: Instruction packaging used in the IA-64 architecture.

As it has already been said, the 5-bit field, named as pointer, serves to indicate the kinds of instructions that are packed. Those 5 bits offer 32 kinds of packaging possible that, in fact, are reduced to 24 kinds, since 8 are not used. Each instruction uses one of the CPU features, which are listed below, and that can be identified in Figure 2 (on next page):

• I Unit: integer data;
• F Unit: floating-point operations;
• M Unit: memory access; and
• B Unit: branch prediction.