Hardware Secrets
Home | Camera | Case | CE | Cooling | CPU | Input | Memory | Mobile | Motherboard | Networking | Power | Storage | Video | Other
Content
Articles
Editorial
First Look
Gabriel’s Blog
News
Reviews
Tutorials
Main Menu
About Us
Awarded Products
Datasheets
Dictionary
Download
Drivers
Facebook
Links
Manufacturer Finder
Newsletter
RSS Feed
Test Your Skills
Twitter
Newsletter
Subscribe today!
Search
Recommended
Upgrading and Repairing PCs (21st Edition)
Upgrading and Repairing PCs (21st Edition), by Scott Mueller (Que Publishing), starting at $26.72


Home » CPU
Inside the Intel Sandy Bridge Microarchitecture
Author: Gabriel Torres 68,405 views
Type: Tutorials Last Updated: December 30, 2010
Page: 4 of 6
The Ring Architecture

Sandy Bridge-based processors will have a ring architecture for the internal components of the CPU to talk to each other. When a component wants to “talk” with another component, it puts the information in the ring and the ring will move this information until it reaches its destination. Components don’t talk to each other directly, they have to use the ring. Components that use the ring include the CPU cores, each L3 memory cache (which is now called Last Level Cache, or LLC, and is not unified, see Figure 5),  the system agent (integrated memory controller, PCI Express controller, power control unit, and display), and the graphics controller.

In Figure 5 you can see the ring (black line) with its “stops” (red boxes). It is important to understand that the ring is physically located over the memory caches (imagine a ski lift where each red box is a stop) – since the illustration is bi-dimensional, you may have the impression that the ring wires run inside the cache, which is not the case.

Also, each last level cache isn’t tied to a particular CPU core. Any core can use any of the caches. For example, in Figure 5, we have a quad-core CPU with four last level caches. Core 1 isn’t linked to cache 1; it can use any of the caches. This also means that any CPU core can access data that is stored in any of the caches.

Sandy Bridge
click to enlarge
Figure 5: The ring architecture (black line with red “stops”)

There are actually four rings: data ring, request ring, acknowledge ring and snoop ring. They run at the same clock rate as the CPU internal clock. It is based on the QPI (QuickPath Interconnect) protocol, the same one used by socket LGA1366 CPUs to talk to the chipset.

Each component decides when to use the ring, if empty, and the ring always choose the shortest path to the destination.

Print Version | Send to Friend | Bookmark Article « Previous |  Page 4 of 6  | Next »

Related Content
  • ECS H67H2-M Motherboard
  • Biostar TP67XE Motherboard
  • Core i5-2500K vs. Phenom II X4 975 BE CPU Review
  • Core i7-2600K CPU Review
  • ECS H67H2-I Motherboard

  • RSSLatest Content
    ASUS ZenFone 5 Smartphone Review
    October 15, 2014 - 7:00 PM
    ASUS AM1M-A Motherboard
    October 15, 2014 - 4:30 AM
    ASRock X99 Extreme4 Motherboard
    October 14, 2014 - 4:10 AM
    Cooler Master Elite 130 Case Review
    October 9, 2014 - 2:46 AM
    ASUS RAMPAGE V EXTREME Motherboard
    October 7, 2014 - 2:50 AM
    ASRock Fatal1ty X99M Killer Motherboard
    October 6, 2014 - 5:40 AM
    ASUS X99-DELUXE Motherboard
    September 30, 2014 - 1:07 AM
    MSI GT70 2PE Dominator Pro Laptop Review
    September 25, 2014 - 1:15 AM







    2004-14, Hardware Secrets, LLC. All rights reserved.
    Advertising | Legal Information | Privacy Policy
    All times are Pacific Standard Time (PST, GMT -08:00)