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Home » CPU
Inside the AMD Bulldozer Architecture
Author: Gabriel Torres 67,098 views
Type: Tutorials Last Updated: August 24, 2010
Page: 2 of 7
Instruction Sets

The Bulldozer architecture, besides being compatible with the standard x86 instructions, will support the following additional instruction sets:

  • SSE4.1 and SSE4.2
  • AVX (Advanced Vector Extensions) with two additional subsets, called XOP and FMA4
  • AES (Advanced Encryption Standard)
  • LWP (Light Weight Profiling)

But what does that mean? Let’s see.

SSE4.1 and SSE4.2

Finally AMD CPUs will support SSE4 instructions. Currently AMD CPUs don’t support these instruction sets, which increase speed in multimedia applications (image and  video processing) that support it. Current AMD CPUs support a proprietary instruction set called SSE4a, which isn’t the same thing as SSE4.

AVX (Advanced Vector Extensions)

A while ago, AMD proposed an SSE5 instruction set. Because Intel decided to create its own implementation of what would be the SSE5 instructions, called AVX (Advanced Vector Extensions), AMD added this instruction set to the Bulldozer architecture.

The AVX instructions will also be supported by forthcoming CPUs from Intel based in their Sandy Bridge architecture, and use the same SIMD (Single Instruction, Multiple Data) concept introduced with the MMX instruction set and used by the SSE (Streaming SIMD Extensions) instructions. This concept consists in using a single big register to store several small-sized data and then process all data with a single instruction, speeding up processing.

The AVX instruction set adds 12 new instructions and increases the size of the XMM registers from 128 bits to 256 bits.

In the Bulldozer architecture, AMD decided to add some of the instructions they had originally proposed for the SSE5 instruction set. Therefore, the AVX implementation in the Bulldozer architecture is more complete than Intel’s. These additional instructions are called the XOP and FMA4 instructions, and a detailed description can be found here. In their Bulldozer presentations AMD is announcing the AVX instruction set as “also” having the FMAC (Fused Multiply Accumulate) subset, but this subset of instructions is actually part of the XOP instructions. The “AMD 4-operand form” being announced in the AMD presentations is simply the new format used by the XOP instructions and mentioning this is also completely redundant.

AES (Advanced Encryption Standard)

This instruction set is already being used in the new Intel CPUs based on the “Westmere” architecture and newer (except Core i3), and consists of six new instructions to deal specifically with encryption. Intel calls this instruction set AES-NI. A detailed description of these instructions can be found here.

LWP (Light Weight Profiling)

The LWP instructions allow programs to easily monitor software performance, which will help developers to fine-tune programs for best performance, for example. This additional instruction set has six new instructions, and a detailed description can be found here.

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