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The Unabridged Pentium 4: IA32 Processor Genealogy
The Unabridged Pentium 4: IA32 Processor Genealogy, by Tom Shanley (Addison-Wesley Professional), starting at $7.44


Home » CPU
Inside Pentium 4 Architecture
Author: Gabriel Torres 220,631 views
Type: Tutorials Last Updated: October 18, 2005
Page: 3 of 7
Memory Cache and Fetch Unit

Pentium 4’s L2 memory cache can be of 256 KB, 512 KB, 1 MB or 2 MB, depending on the model. L1 data cache is of 8 KB or 16 KB (on 90 nm models).

As we explained before, the L1 instruction cache was moved from before the fetch unit to after the decode unit using a new name, ”trace cache“. So, instead of storing program instructions to be loaded by the fetch unit, the trace cache stores microinstructions already decoded by the decode unit. The trace cache can store up to 12 K microinstructions and since Pentium 4 microinstructions are 100-bit wide, the trace cache is of 150 KB (12,288 x 100 / 8).

The idea behind this architecture is really interesting. In the case of a loop on the program (a loop is a part of a program that needs to be repeated several times), the instructions to be executed will be already decoded, because they are stored already decoded on the trace cache. On other processors, the instructions need to be loaded from L1 instruction cache and decoded again, even if they were decoded a few moments before.

The trace cache also has its own BTB (Branch Target Buffer) of 512 entries. BTB is a small memory that lists all identified branches on the program.

As for the fetch unit, its BTB was increased to 4,096 entries. On Intel 6th generation processors, like Pentium III, this buffer was of 512 entries and on Intel 5th generation processors, like the first Pentium processor, this buffer was of 256 entries only.

In Figure 3 you see the block diagram for what we were discussing. TLB means Translation Lookaside Buffer.

Pentium 4 Architecture
click to enlarge
Figure 3: Fetch and decode units and trace cache.

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