|Inside AMD K10 Architecture|
K10 is the name of the new architecture that new processors from AMD will be using, like the forthcoming Phenom and the Opteron based on the much expected “Barcelona” core. In fact, a lot of people are making a big confusion calling K10 architecture as “Barcelona,” while Barcelona is only one of the CPUs that will use this new architecture. In this tutorial we will explain what is new on the K10 architecture and will also present a complete AMD roadmap showing all products based on K10 architecture that are planned so far.
The new K10 architecture is based on the K8 (a.k.a. AMD64) architecture with some enhancements. Thus we recommend you to read our Inside AMD64 Architecture before continuing to read the present tutorial. By the way, AMD never released an architecture called K9, from K8 they jumped to K10.
The foil presented in Figure 1 shows the main enhancements K10 microarchitecture brings over K8.
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Figure 1: K10 microarchitecture enhancements over K8.
The main points that were enhanced were:
- The fetch unit fetches 32 bytes (256 bits) of data per clock cycle from the L1 instruction cache – this is the double CPUs based on K8 architecture could fetch per clock cycle. Intel CPUs based on Core microarchitecture, like Core 2 Duo, also fetches 32 bytes per clock cycle.
- The use of a true 128-bit internal datapath. On previous CPUs based on K8 microarchitecture the internal datapath was of 64 bits only. This was a problem for SSE instructions, since SSE registers, called XMM, are 128-bit long. So, when executing an instruction that manipulated a 128-bit data, this operation had to be broke down into two 64-bit operations. The new 128-bit datapath makes K10 microarchitecture faster to process SSE instructions that manipulate 128-bit data compared to K8 microarchitecture. Intel processors based on Core microarchitecture (Core 2 Duo, for example) also have 128-bit internal datapaths, while Intel processors based on Netburst microarchitecture (Pentium 4 and Pentium D) have a 64-bit internal datapaths. AMD is calling this new feature “AMD Wide Floating Point Accelerator.”
In Figure 2, you can see a list of new features introduced by K10 architecture. We will be explaining each one of them in the next pages.
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Figure 2: New features introduced by K10 architecture.
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