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How Analog-to-Digital Converter (ADC) Works
Author: Gabriel Torres 674,979 views
Type: Tutorials Last Updated: April 21, 2006
Page: 8 of 10
Integrator-Based Designs

There are a few ways of designing analog-to-digital converters using an integrator. Let’s take a look at two of them, single-slope ADC and delta-sigma ADC.

Single-Slope ADC

In Figure 10, you can see a single-slope ADC. If you pay close attention, you will see that it is very similar to a ramp counter ADC, as it uses a counter, but instead of using a DAC for generating the comparison voltage, it uses a circuit called integrator, which is basically formed by a capacitor, a resistor and an operational amplifier (op amp). The MOSFET transistor makes the necessary control circuit.

Single-Slope ADC
click to enlarge
Figure 10: Single-slope ADC.

The integrator produces a sawtooth waveform on its output, from zero to the maximum possible analog voltage to be sampled, set by -Vref. The minute the waveform is started, the counter starts counting from 0 to 2^n-1, where n is the number of bits implemented by the ADC. When the voltage found at Vin (the analog signal) is equal to the voltage achieved by the triangle waveform generated by the integrator, the control circuit captures the last value produced by the counter (by trigging the output buffer clock pin), which will be the digital correspondent of the analog sample being converted. At the same time, it resets the counter and the integrator, starting the conversion of the next sample.

Like the successive approximation ADC, this circuit uses an output buffer, meaning that the last converted value can be read while the ADC is converting the current value.

Even though its design is simpler than ramp counter design, it is still based on a counter, and thus suffering from the same basic problem found on ramp counter design: speed. It requires up to 2^n-1 clock cycles to convert each sample. For an eight-bit ADC, it would take up to 255 clock cycles to convert a single sample. For a 16-bit ADC it would take up to 65,535 clock cycles to convert one sample.

Dual-Slope ADC

Another popular design based on this one is called dual-slope ADC, which solves an inherent single-slop problem called calibration drift, which leads to inaccuracy over time because the integrator isn’t linked to the clock signal (i.e., the sawtooth waveform isn’t synchronized with the counter clock).

A classic dual-slope ADC can be seen in Figure 11.

Dual-Slope ADC
click to enlarge
Figure 11: Dual-slope ADC.

The analog switch first connects Vin to the integrator. With that, the integrator starts generating the sawtooth waveform, and the switch position will remain set at Vin during a fixed number of clock cycles. When this number of clock cycles is reached, the analog switch moves its position to allow –Vref to enter the integrator. Since –Vref is a negative voltage, the sawtooth waveform goes towards zero, using a number of clock cycles proportional of the Vin value.

For a better understanding, see Figure 12, where we show the waveform at the integrator output. So, T1 is fixed, while T2 duration is proportional to the value of Vin. Vin sets the slope angle: the higher Vin is, the higher the angle will be.

Dual-Slope ADC
click to enlarge
Figure 12: Waveform found at the integrator output.

T2 = T1 x Vin / Vref.

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