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HyperTransport┬┐ System Architecture
HyperTransport┬┐ System Architecture, by Don Anderson (Addison-Wesley Professional), starting at $0.16
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Everything You Need to Know About the HyperTransport Bus
Author: Gabriel Torres 233,744 views
Type: Tutorials Last Updated: October 13, 2011
Page: 2 of 4
HyperTransport 1.x

The HyperTransport bus can operate under several different clock and width (i.e., the number of bits that are transmitted per time) configurations. This is probably where a lot of misconceptions and mistakes regarding HyperTransport are said and written.

The HyperTransport is a bus created by a consortium comprised of several companies including AMD, NVIDIA, and Apple. This bus can be used on several applications, and it is not limited to AMD processors.

This means that the actual configuration of the HyperTransport bus will depend on the hardware developer.

Also, some developers announce an exaggerated transfer rate of the HyperTransport bus they are using.

AMD processors use 16-bit links, even though HyperTransport allows the use of 32-bit links.

HyperTransport 1.x (“HT1”) is used on all socket 754 processors and socket AM2 Sempron processors. (Other AM2-based processors use HyperTransport 2.0.)

Here is a breakdown of all possible clock and transfer rates on HyperTransport 1.x:

  • 200 MHz = 400 MT/s = 800 MB/s
  • 400 MHz = 800 MT/s = 1,600 MB/s
  • 600 MHz = 1,200 MT/s = 2,400 MB/s
  • 800 MHz = 1,600 MT/s = 3,200 MB/s

HyperTransport transfers two data per clock cycle, a concept also known as DDR, double data rate.

The formula to find the maximum theoretical transfer rate is:

Transfer rate = width (number of bits) x clock x number of data per clock cycle / 8

Thus, with socket 754 processors, the HyperTransport bus can work up to 800 MHz or 3,200 MB/s. Some people advertise this clock and transfer rate using other numbers, generating a lot of confusion in the market.

Some say that the clock rate used by HyperTransport 1.x is 1,600 MHz. This occurs because since on each clock cycle two data are transferred, the performance obtained is similar to 1,600 MHz clock rate, transferring only one data per clock cycle. In the end, the transfer rate will be the same, as in the above formula instead of using “2” for “number of data per clock cycle,” it will use “1” instead. This is the same thing that happens with DDR memories, where the announced clock rate is double the actual clock rate (e.g., DDR3-1600 memories work, in fact, at 800 MHz, transferring two data per clock cycle).

AMD says that the clock rate used by its socket 754 CPUs is 1,600 MT/s. MT/s stands for Mega Transfers per second, or Millions of Transfers per second. This is the correct way to express the above idea. Transfers per second are equal to the clock rate times the number of data transferred per clock cycle.

Some say that the maximum transfer rate of HyperTransport 1.x is 6,400 MB/s. This occurs because the announced transfer rate is for each datapath (i.e., 3,200 MB/s for the input datapath and 3,200 MB/s for the output datapath), so some people simple multiply the transfer rate by two to cover the two datapaths. We don’t agree with this methodology. In brief, it is as if we said that a highway has a speed limit of 130 mph just because there is a speed limit of 65 mph in each direction. It doesn’t make any sense.

Another misunderstanding is saying that the external bus or FSB (Front Side Bus) of Athlon 64 (or any other CPU based on HyperTransport 1.x bus) is 1,600 MHz. This is partially correct. We can say this regarding I/O operations, but not for memory, as processors based on AMD64 architecture have two separated external busses, as we discussed. Thus, it is better to say “HyperTransport” or “HT” rather than “external bus” or “FSB” in order to avoid confusion.

It is important to note that AMD processors can work with several other clock rates below the announced 1,600 MT/s (800 MHz). In fact, they can work with any of the speeds on the list published above.

The chipset can negotiate a lower clock rate with the CPU and even an eight-bit width instead of the default 16-bit one. In fact, when the first Athlon 64 chipsets came out, VIA claimed that their chipset for the Athlon 64, the K8T800, was superior to the competition for working with the HyperTransport bus at 1,600 MT/s. VIA accused competing products (without mentioning names) of not working at the maximum transfer rate that the HyperTransport allows, but rather at one of those inferior rates, or even using eight-bit instead of 16-bit links.

At http://www.hypertransport.org, HyperTransport’s official website, you will see that they announce a maximum transfer rate of 12.8 GB/s for the HyperTransport 1.x. This maximum transfer rate is achieved by using 32-bit links. As we explained, AMD processors use 16-bit links. However, if you do the math, you will find 6,400 MB/s (32 bits x 800 MHz x 2 / 8). Here the consortium doubled the maximum transfer rate just because there are two datapaths available (one for transmitting data and another for receiving it). As we said before, we do not agree with this methodology of calculating transfer rates.

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