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Home » CPU
Everything You Need to Know About the CPU C-States Power Saving Modes
Author: Gabriel Torres 429,495 views
Type: Tutorials Last Updated: September 4, 2008
Page: 4 of 6
C3 State

C3, also known as Sleep state, was first used on Pentium II from Intel and the very first Athlon CPU from AMD. Interesting enough this mode isn’t available on Core 2 Duo CPUs manufactured under 65-nm process – i.e., model numbers starting with “4” or “6” –, but these CPUs implement other “extended” states (C1E and C2E) mentioned before. Core 2 Duo manufactured under 45-nm process – i.e., model numbers starting with “7” or “8” – do have this mode back again.

As we explained, when the CPU is in the Halt (C1) or in the Stop Grant (C2) states the CPU internal clock is cut from almost all units inside the CPU, making them to stop and thus consume less power. On these states, however, two internal CPU units are kept running: the bus interface unit and the APIC, Advanced Programmable Interface Controller. These units are kept running so the CPU can deal with important requests coming from the CPU external bus and can handle interruptions.

The next state, Sleep (C3), cuts all internal clock signals from the CPU, including the clocks from the bus interface unit and from the APIC. This means that when the CPU is in the Sleep mode it can’t answer to important requests coming from the CPU external bus nor interruptions.

Intel CPUs and Turion 64 from AMD allow a C3 sub-mode called Deep Sleep, where the CPU external clock is also stopped, thus saving more power.

The way the CPU enters C3 state depends on the manufacturer. Intel CPUs add an extra pin, called SLP (or DPSLP, depending on the CPU model), which must be activated when the CPU is in C2 state in order to switch the CPU into C3 state. So first STPCLK pin must be activated and then one should activate the SLP pin. Entering the Deep Sleep state is achieved by simply cutting the external clock signal.

On AMD CPUs the C3 state is entered by simply reading a register from the ACPI (Advanced Control Power Interface), circuit that is physically located on the chipset. If the program, reads the PLVL_2 register, the chipset will activate the STPCLK pin putting the CPU into Stop Grant (C2) mode while if the program reads the PLVL_3 register the chipset will activate the STPCLK pin putting the CPU into Sleep (C3) mode.

AMD mobile CPUs (Turion 64) support a sub-mode called AltVID that allows the reduction on the CPU voltage while they are in the C3 mode.

Also don’t forget that Turion 64, 65-nm Athlon X2 and Phenom CPUs also have a mode called C1E that isn’t related to Intel’s C1E that puts the CPU in a mode identical to C3. The difference between AMD’s C1E and C3 states is basically how the CPU enters the Sleep state: while on the traditional C3 state the CPU must be put in that state usually by a command issued by the operating system, on C1E the CPU enters the Sleep state automatically when all cores are at Halt (C1) state.

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