The C2 state was also introduced with 486DX4, by adding one extra pin to the CPU, called “STPCLK” (“Stop Clock”). When this pin is activated, the CPU core clock is cut.

As you can see, C2 state is somewhat similar to C1 state: both cut the CPU core clock. The difference between them is how the CPU achieves this: C1 state is activated by software (thru an “HLT” instruction) while C2 state is activated by hardware (by sending a signal to a CPU pin called “STPCLK”).

Like it happens when the CPU is in the C1 state, the CPU internal clock isn’t completely stopped when the CPU enters C2 state: the bus interface and APIC units are still being fed with the CPU internal clock rate. This is done to allow the CPU to temporarily exit the C2 state to take care of an important request coming from the CPU external bus.

Since the clock signal is stopped for almost all CPU internal units, they stop running, making them to consume less power.

There are two sub-modes for the C2 state: Stop Grant and Stop Clock. Stop Grant is achieved after the “STPCLK” pin is activated. As explained, in this mode the CPU core clock is stopped but the clock generator chip (also known as PLL, Phase-Locked Loop) is still active and generating the external bus reference clock, i.e. the CPU external clock.

486DX4, Pentium, Pentium MMX, K5, K6, K6-2 and K6-III could go one step further and enter a deeper sub-state called Stop Clock where the clock generator chip would be turned off and thus the external clock signal would also be turned off, thus saving more energy. Current CPUs don’t have the Stop Clock mode inside the C2 State but on the C3 Deep Sleep state.

Like the Halt (C1) state, the CPU can temporarily leave the Stop Grant (C2) state to deal with an important request coming from thru the CPU external bus. This temporary leave is called Stop Clock Snoop State, HALT/Grant Snoop State or simply Snoop State and during its duration the CPU clock is restored. After the CPU has handled the request, it goes automatically back to the Stop Grant (C2) state.

Core 2 Duo CPUs brought an advanced Stop Grant state called Extended Stop Grant or C2E, which also reduces the CPU voltage besides stopping the CPU internal clock. If this mode is enabled on the motherboard BIOS, the CPU will enter this mode instead of the traditional Stop Grant (C2) mode when STPCLK pin is activated. Otherwise the CPU will continue to use the standard Stop Grant mode.

This CPU also introduced the Extended Halt/Stop Grant Snoop state, which allows the CPU to temporarily exit C1E or C2E modes to respond to an important request coming from the CPU external bus, but keeping the CPU lower voltage instead of restoring the CPU full voltage.