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Breaking Through the BIOS Barrier: The Definitive BIOS Optimization Guide for PCs
Breaking Through the BIOS Barrier: The Definitive BIOS Optimization Guide for PCs, by Adrian Wong (Prentice Hall PTR), starting at $20.00
Home » Motherboard
BIOS Setup
Author: Gabriel Torres
Type: Tutorials Last Updated: July 1, 2004
Page: 9 of 13
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Advanced Chipset Setup (Cont.)

Generally, options related to the time base must be set up in the same way as the wait states - the shorter the time, the higher the performance. But, in order to do that, you must find the precise setup value as we discussed previously. The following options may be set up similarly to the wait states:

  • RAS to CAS Delay or Fast RAS to CAS Delay: States how many clock pulses are there between the RAS signal and the CAS signal, controlling the RAM memory access.
  • DRAM RAS Precharge Time: Number of CPU clocks allocated for the RAS signal (controlling memory access) to accumulate its charge before the DRAM is refreshed (Memory refresh is a cyclic memory scan done in order to recharge the stored values).
  • DRAM R/W Leadoff Timing: Number of CPU clocks needed before each read from or write to the memory.

We will discuss below other common options to be found in the chipset advanced setup.

  • DRAM Speed: To be set up according to access time of installed memories.
  • DRAM Speculative Leadoff: Motherboard chipset will pass the read command to memory slightly before it has fully decoded the address, thus speeding up the read process. We recommend you enable this option.
  • Turn-around Insertion: Inserts one wait state to the access to two consecutive memory data. Disable this option to suppress this wait state, increasing the PC performance.
  • Read-around Write: If a data is read from address of latest write to memory, the memory controller embedded in motherboard chipset may pass the data without an actual memory read, as data is still held in the chipset internal buffer. Enable this option to get some performance improvement.
  • I/O Recovery Time or AT Cycle Wait State or AT Cycle Between I/O Cycles or 8 Bit I/O Recovery Time or 16 Bit I/O Recovery Time: Set up additional wait states to be used in the access to devices installed in the ISA bus. As wait states utilization degrades performance, we suggest you disable these options (or set them up at 0 wait states) or, in case it is not possible, set the utilization of just one wait state.
  • ISA Line Buffer: Enables a data buffer to ISA bus increasing its performance. We suggest you enable this option.
  • Memory Hole or Memory Hole At 15 MB Add: Creates a memory hole between 15M and 16M in order to have the PC compatible with some old ISA video boards using this memory area. As this options results in a loss of 1 MB of memory, we suggest you keep it disabled.
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