As you can see this will be Intel’s first desktop processor to include a memory controller inside the CPU, thing that AMD has being doing since 2003 with their Athlon 64 CPU’s. This procedure increases the memory performance (i.e. memory transfer rate), as the memory controller will be as much close to the CPU cores as possible, cutting delays involved in the process of going out from the CPU to talk to the memory controller on the motherboard.

Nehalem will have a DDR3 memory controller embedded, supporting DDR3-800, DDR3-1064 and DDR3-1333. But is really new in the computer industry is the use of a triple-channel architecture, i.e. three memory modules will be accessed at the same time, transferring 192 bits per cycle instead of 128 on dual-channel configurations and 64 on single-channel configurations, providing a 50% performance increase compared to dual-channel architecture. When three DDR3-1333 modules are installed, available bandwidth will increase to 31,992 MB/s compared to 21,328 MB/s on current dual-channel configurations using the same memories.

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Figure 5: Embedded triple-channel DDR3 memory controller.

AMD uses HyperTransport bus to connect the CPU to the chipset, and Intel will be using their new QuickPath bus, and each Nehalem CPU will have two QuickPath busses, one for connecting the CPU to the chipset and another to connect the CPU to another CPU, for multi-CPU platforms (see Figure 6). At this time Intel didn’t tell much about QuickPath (clock rates, number of bits transferred per clock cycle, etc); they only told us that this bus makes up to 6.4 billion transfers per second per link and that the CPU will have an available bandwidth of 25.6 GB/s per link. Each link will probably have separated datapaths for transferring and receiving data, so this number is probably inflated, i.e. probably each datapath will have a maximum transfer rate of 12.8 GB/s.

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Figure 6: The new QuickPath external bus.