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Recommended Book
The Winn L. Rosch Hardware Bible (6th Edition)
By Winn L Rosch
Que
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Home » CPU
Details on the Forthcoming Intel Nehalem Processor
Author: Gabriel Torres
Type: Articles Last Updated: March 17, 2008
Page: 1 of 3
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Introduction

Intel released today more details on their forthcoming Nehalem processor, which should arrive on the market by the end of this year. Main features will include a triple-channel integrated memory controller, three cache levels, the return of HyperThreading technology, a new external bus called QuickPath and more. Read on to learn everything you need to know about this future CPU.

“Nehalem” is just a codename and not the final name for this new CPU series and at this point we don’t know yet what its commercial name will be. One year ago Intel gave us an overall picture of this future CPU, but now they disclosure several more details.

Below we summarized a list of Nehalem main features, and we will explain what each one of them mean throughout this article:

  • Based on Intel Core microarchitecture.
  • Two to eight cores.
  • Integrated DDR3 triple-channel memory controller.
  • Individual 256 KB L2 memory caches for each core.
  • 8 MB L3 memory cache.
  • New SSE 4.2 instruction set, with the addition of seven new instructions for string and text processing, collectively called “Application Target Accelerators”.
  • Two-way simultaneous multi-threading (SMT).
  • Enhancements on the microarchitecture (4-way dispatch unit).
  • Enhancements on the prediction unit, with the addition of a second Branch Target Buffer (BTB).
  • A second 512-entry Translation Look-aside Buffer (TLB).
  • Improved virtualization performance.
  • New QuickPath external bus (two links per CPU socket).
  • 45 nm manufacturing technology.

Intel Nehalem CPU
click to enlarge
Figure 1: Nehalem CPU main specs.

Nehalem will be a 45-nm CPU based on Intel Core Microarchitecture. In order words, a CPU based on the current Core 2 Duo CPUs.

On the cache memory side Intel will use the same cache arrangement AMD is using on their Phenom CPUs, i.e. individual L2 caches for each core and a shared L3 memory cache. Each L2 memory cache will be of 256 KB and the L3 cache will be of 8 MB (see Figure 2). L1 cache remains the same as Core 2 Duo (64 KB, 32 KB for instructions and 32 KB for data).

Intel Nehalem CPU
click to enlarge
Figure 2: Nehalem cache architecture.

Core 2 Duo processors have only one L2 memory cache, which is shared among all CPU cores, but quad-core CPUs from Intel like Core 2 Quad and Core 2 Extreme have two L2 caches, each one shared by each group of two cores. For a better understanding we summarize the available cache architectures on Figures 3 and 4.

Intel Nehalem CPU
click to enlarge
Figure 3: A comparison between cache architectures.

Intel Nehalem CPU
click to enlarge
Figure 4: A comparison between cache architectures.

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