How The Memory Cache Works | Hardware Secrets

Below we present you a reference table containing the main memory cache specs for the main CPUs available on the market today.

CPU	L1 Instruction	L1 Data	L2
Athlon 64	64 KB 2-way set associative 64-byte lines 128-bit datapath with L2 128-bit datapath with fetch unit	64 KB 2-way set associative 64-byte lines 128-bit datapath with L2	512 KB or 1 MB 16-way set associative 64-byte lines 128-bit datapath with L1 data 128-bit datapath with L1 instruction
Athlon 64 FX	64 KB per core 2-way set associative 64-byte lines 128-bit datapath with L2 128-bit datapath with fetch unit	64 KB per core 2-way set associative 64-byte lines 128-bit datapath with L2	1 MB per core 16-way set associative 64-byte lines 128-bit datapath with L1 data 128-bit datapath with L1 instruction
Athlon 64 X2	64 KB per core 2-way set associative 64-byte lines 128-bit datapath with L2 128-bit datapath with fetch unit	64 KB per core 2-way set associative 64-byte lines 128-bit datapath with L2	512 KB or 1 MB per core 16-way set associative 64-byte lines 128-bit datapath with L1 data 128-bit datapath with L1 instruction
Sempron (sockets 754 and AM2)	64 KB 2-way set associative 64-byte lines 128-bit datapath with L2 128-bit datapath with fetch unit	64 KB 2-way set associative 64-byte lines 128-bit datapath with L2	128 KB or 256 KB 16-way set associative 64-byte lines 128-bit datapath with L1 data 128-bit datapath with L1 instruction
Opteron	64 KB per core 2-way set associative 128-bit datapath with L2 128-bit datapath with fetch unit	64 KB per core 2-way set associative 64-byte lines 128-bit datapath with L2	1 MB per core 16-way set associative 64-byte lines 128-bit datapath with L1 data 128-bit datapath with L1 instruction
Pentium 4	N/A *	8 KB 4-way set associative 64-byte lines 256-bit datapath with L2	256 KB, 512 MB or 1 MB 8-way set associative 128-byte lines 64-bit datapath with fetch unit 256-bit datapath with L1 data
Pentium D	N/A *	16 KB 4-way set associative 64-byte lines 256-bit datapath with L2	1 MB or 2 MB per core 8-way set associative 128-byte lines 64-bit datapath with fetch unit 256-bit datapath with L1 data
Core 2 Duo	32 KB 64-byte lines 256-bit datapath with fetch unit	32 KB 64-byte lines 256-bit datapath with L2	2 MB or 4 MB 8-way set associative 64-byte lines 256-bit datapath with L1 data
Pentium Dual Core	32 KB 64-byte lines 256-bit datapath with fetch unit	32 KB 64-byte lines 256-bit datapath with L2	1 MB 8-way set associative 64-byte lines 256-bit datapath with L1 data

* There is a 150 KB trace cache on these processors. This cache is located between the decoder unit and the execution unit. Thus the fetch unit grabs data directly from L2 memory cache.

We didn’t include Xeon and Celeron processors on the above table because there are several different Xeon and Celeron models around based on different architectures. Celeron and Xeon based on Netburst microarchitecture (i.e. based on Pentium 4) will have the same specs as Pentium 4 but with different L2 cache size, while Celeron and Xeon based on Core microarchitecture (i.e. based on Core 2 Duo) will have the same specs as Core 2 Duo but with different L2 cache size.