Just to remember, memory cache is a high-speed memory (static RAM or SRAM) embedded inside the CPU used to store data that the CPU may need. If the data required by the CPU isn’t located in the cache, it must go all the way to the main RAM memory, which reduces its speed, as the RAM memory is accessed using the CPU external clock rate. For example, on an AMD 3 GHz CPU, the memory cache is accessed at 3 GHz but the RAM memory is accessed at 800 MHz (if you are using DDR2-800 memories) or less.

On Pentium D and AMD dual-core CPUs based on K8 architecture each CPU core has its own L2 memory cache. On Intel dual-core CPUs based on Core and Pentium M microarchitectures, there is only L2 memory cache, which is shared between the two cores.

Intel says that this shared architecture is better, because on the separated cache approach at some moment one core may run out of cache while the other may have unused parts on its own L2 memory cache. When this happens, the first core must grab data from the main RAM memory, even though there was empty space on the L2 memory cache of the second core that could be used to store data and prevent that core from accessing the main RAM memory. So on a Core 2 Duo processor with 4 MB L2 memory cache, one core may be using 3.5 MB while the other 512 KB (0.5 MB), contrasted to the fixed 50%-50% division used on other dual-core CPUs.

On the other hand, current quad-core Intel CPUs like Core 2 Extreme QX and Core 2 Quad use two dual-core chips, meaning that this sharing only occurs between cores 1 & 2 and 3 & 4. In the future Intel plans to launch quad-core CPUs using a single chip. When this happens the L2 cache will be shared between the four cores.

On Figure 3 you can see a comparison between these three L2 memory cache solutions.

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Figure 3: Comparison between current L2 memory cache solutions on current multi-core CPUs.

K10 architecture adds a shared L3 memory cache inside the CPU. This is shown on Figure 4. The size of this cache will depend on the CPU model, just like what happens with the size of L2 cache.

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Figure 4: K10 cache architecture.

AMD calls this approach as “Balanced Smart Cache”.

By the way, L1 memory cache continues unaltered: 64 KB for instructions and 64 KB for data per core (on Figure 1 AMD shows “512 KB”, but this is the total figure for a quad-core CPU).