As for the next Intel microarchitecture, Intel revealed some key points of the forthcoming Nehalem microarchitecture.

Concretely what we know so far:

• It will be based on Core microarchitecture.
• Capacity of up to eight cores per CPU.
• It will bring Hyper-Threading to Core microarchitecture. As Hyper-Threading is a feature available only on Netburst microarchitecture (used on Pentium 4), it was renamed to Simultaneous Multi-Threading (we need to wait and see if this will be the final name they will use). This technology simulates two cores for each CPU core. So a quad-core CPU would be recognized as an eight-core CPU by the operating system.
• Some models will have an integrated video controller. Yes, on-board video controlled by the CPU. It should be a lot faster than the current on-board video solutions controlled by the chipset. With the acquisition of ATI by AMD, we should expect something similar coming from AMD side as well. This isn't a new idea, by the way. Cyrix used this idea back in 1997 on their MediaGX CPU, which had an embedded video and memory controller. Cyrix division in charge of MediaGX was sold to National, which developed its Geode processor line based on MediaGX. Even more curiously, AMD bought Geode line from National in 2003.
• It will have the north bridge chip embedded in the CPU, just like what happens with AMD64 CPUs.
• Multi-level cache, whatever this is. Probably each core will have its own L2 memory cache plus an L3 cache that will be shared by all cores. This is just a speculation; we need to wait for more details.

Intel listed several generic and very obvious features that simply means nothing to us, so we will need to wait until they disclosure more on Nehalem microarchitecture to be able to translate what they mean by this:

• “Dynamically scalable for leadership performance on demand with energy efficiency”.
• “Leadership system and memory bandwidth”
• “Performance enhanced dynamic power management”
• “New system architecture for next-generation Intel processors and platforms”
• “Dynamically managed cores, threads, cache, interfaces and power”