| Inside AMD64 Architecture |
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| $ Check REAL-TIME pricing for AMD Athlon™ 64 X2 6000+, 3.0 GHz (ADX6000CZBOX) Boxed Processor $ |
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| AMD64 Main Features |
When it was released with Athlon 64, AMD64 architecture brought a new 64-bit mode for x86 instructions. This mode is called x86-64 by AMD and what it does is to expand the existing 32-bit registers into 64-bit ones. All AMD64 CPUs have sixteen 64-bit general purpose registers when running under x86-64 mode. Under this mode the CPU address bus is also expanded from 32 to 40 bits, enabling the CPU to directly access up to 1 TB of RAM (2^40). Also under this mode the CPU can access up to 256 TB of virtual memory (2^48). Virtual memory is a technique that allows the CPU to simulate more RAM memory that the computer has by creating a file on the hard disk drive called swap file.
Intel copied all these features, so they are not an exclusive feature from AMD anymore. However, while all AMD64 CPUs support the x86-64 mode (the exception goes for the early socket 754 Sempron CPUs), not all recent CPUs from Intel support it.
To use this mode, however, it is necessary to run a 64-bit operating system. Don’t expect to access more than 4 GB RAM with an Athlon 64 running regular Windows XP, for example, since regular Windows XP runs under 32-bit mode. For a more detailed explanation about the 64-bit mode, read our tutorial on this subject.
As you may have noticed, AMD64 memory controller works with DDR or DDR2 technology. Dual Data Rate technology works by transferring two data per clock cycle. So when using your Athlon 64 with DDR400/PC3200 memories, for example, the CPU accesses them at 200 MHz and not at 400 MHz (DDR and DDR2 memories are rated with double the real clock rate they use).
All AMD64 CPUs have one 64 KB L1 instruction cache and one 64 KB L1 data cache. The L2 memory cache varies according to the CPU model. On dual-core CPUs the L2 cache is separated, i.e. each core has its own L2 memory cache. On the latest Intel CPUs (Core Duo and Core 2 Duo) the CPU has only one L2 cache, which is shared by both cores (Intel claims that this approach improves performance). |
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