The sigma-delta ADC – also called delta-sigma, 1-bit ADC or oversampling ADC – uses a different approach. We can divide it into two major blocks: analog modulator, which takes the analog signal and converts it into a stream of bits, and digital filter, which converts the serial stream from the modulator into an “usable” digital number.

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Figure 13: Block diagram of a sigma-delta ADC.

The analog modulator is somewhat similar to a dual-slope ADC, however using a 1-bit DAC as a feedback loop. The basic sigma-delta modulator design can be found on Figure 14.

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Figure 14: Sigma-delta ADC analog modulator basic design.

The analog signal will make the first op amp, which is a summing integrator, to create a sawtooth waveform proportional to the analog signal voltage. This sawtooth waveform found on the integrator output is then compared with zero volts by the second op amp, which is a comparator. It can be considered a 1-bit ADC, since its output will have only two states, high or low, depending whether the integrator output is positive or negative. The comparator output is stored on the D-type flip-flop, which is a one-bit static memory. This flip-flop is clocked at a very high frequency.

Then the flip-flop output is used to feedback the circuit thru a one-bit DAC. This one-bit DAC will basically convert the “0” or “1” stored at the flip-flop into a positive or negative reference voltage to be added to the input of the summing integrator.

So the summing integrator will sum the next sample with the result of the previous sample (a positive or a negative voltage), aiming to maintain zero at the integrator output.

The result is that at the flip-flop output we will have a series of zeros and ones that correspond the sampled data: the bitstream average level represents the analog input signal average voltage.

Since the clock rate used at the flip-flop is very high, data is sampled many times over, a technique known as oversampling. The higher the clock, the higher the precision of the sigma-delta ADC.

In real-world applications, the flip-flop clock rate will be 64 times higher than the sampling rate (i.e., a oversampling rate of 64). So, for a 44,100 Hz sampling rate, the flip-flop clock rate will be of 2,822,400 Hz.

Another way to increase the ADC precision and thus reducing noise is to implement a second summing integrator between the original integrator and the comparator. This implementation would be called second order sigma-delta ADC. Commercial hi-end ADCs for audio application can use a fifth order analog modulator.

The problem with sigma-delta ADCs would be that with using just one bit the SNR would be too low. If you remember our formula SNR = 6.02 x n + 1.76 dB, sigma-delta ADCs would have a SNR of only 7.78 dB.

However, due to oversampling, the quantization noise is thrown to the high frequencies of the spectrum, and not spread all over the spectrum as it occurs with other designs. This effect is called shaped noise. With all the noise concentrated in a specific portion of the spectrum – on a frequency range above the sampled data –, is quite easy to construct a filter to remove it, thus improving SNR. This kind of filter is known as low pass filter (which allows only frequencies below a certain trigger frequency to pass thru it) and this filtering is done on the digital filtering stage.

The use of this kind of filter improves the SNR in 9 dB for every doubling of the clock rate used (9 dB/octave). Without it SNR improves 3 dB/octave only.

So, a first order sigma-delta ADC with an oversampling rate of 64 (2^6) would have a SNR of 54 dB (9 dB x 6).

If we use the SNR formula again, we will come to the conclusion that the effective number of bits (ENOB) can be calculated using:

ENOB = (SNR – 1.76 dB) / 6.02

This means that a first order sigma-delta ADC with an oversampling rate of 64 has the same performance of a multi-bit ADC with a resolution of 8 bits – but using only one bit!

Increasing the number of summing integrators also improves SNR. The SNR improvement can be calculated by the formula 6 x L + 3 dB, where L is the order number. So a second order sigma-delta ADC provides a SNR of 15 dB/octave, a third order provides a SNR of 21 dB/octave, a fourth order a SNR of 27 dB/octave and a fifth order a SNR of 33 dB/octave.

An easier way to calculate the effective number of bits it thru the formula:

ENOB = ((L + 0.5) x n) + 1

Where L is the order number of the sigma-delta ADC and n is the oversampling factor given by 2^n; for a 64x oversampling, n would be 6.

So a second order sigma-delta ADC with a 64x oversampling achieves an effective number of bits of 16 (a 98 dB SNR), thus achieving the same performance of a conventional 16-bit ADC with a simpler (and cheaper) construction.

The next step is to know what digital number the bitstream found at the analog modulator represents, what is done by the digital filtering block, which does also the low pass filtering already explained.

Since the bitstream is oversampled (i.e. its clock is higher than the sampling rate), this stage also “reduces” its clock rate to the sampling rate. This process is known as decimation.

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Figure 15: Block diagram of the sigma-delta digital filter.