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 Author: Gabriel Torres 673,850 views Type: Tutorials Last Updated: April 21, 2006 Page: 7 of 10 Select Page to Load Introduction How It Works: Sampling How It Works: Resolution Surround Audio: Audio Compression Inside an ADC Parallel Design DAC-Based Designs Integrator-Based Designs Sigma-Delta ADC ADC On the PC
DAC-Based Designs

There are a few ways to design an ADC using a DAC as part of its comparison circuit. We will present you two of them: ramp counter and successive approximation.

Ramp counter ADC, also called digital ramp ADC, is shown in Figure 8. Vin is the analog input and Dn through D0 are the digital outputs. The control line found on the counter turns on the counter when it is low and stops the counter when it is high.

click to enlarge

The basic idea is to increase the counter until the value found on the counter matches the value of the analog signal. When this condition is met, the value on the counter is the digital equivalent of the analog signal.

It requires a START pulse for each analog voltage you want to convert into digital. The END signal represents the end of the conversion for each individual voltage (each sample), and not for the entire analog signal. Each clock pulse moves the counter. Supposing an 8-bit ADC, for converting the analog value for ”128“ into digital, for example, it would take 128 clock cycles.

It works by counting from 0 to the maximum possible value (2^n-1) until it ”finds“ the correct digital value for the analog voltage present at Vin. When this is true, the END signal is given and the digital value for Vin is for at Dn through D0.

So the main problem with this circuit is that it is very slow, as it would require up to 2^n-1 clock cycles to convert each sample. For an eight-bit ADC, it would take up to 255 clock cycles to convert a single sample. For a 16-bit ADC it would take up to 65,535 clock cycles to convert one sample.

The second classical ADC circuit using DAC design is called successive approximation, which is the most used one, shown in Figure 9. Vin is the analog input and Dn through D0 are the digital outputs. As you can see, it uses a buffer, so the digital data is still available while the converter is processing the next sample. SAR stands for Successive Approximation Register. It has the same control signals as the ramp counter ADC: START, which commands the ADC to start the conversion, CLOCK and END, which tells us that the conversion of that particular sample has finished.

click to enlarge

While the ramp counter ADC does the analog-to-digital conversion counting from 0 to the maximum possible value (2^n-1) until it ”finds“ the correct digital value for Vin, the successive approximation ADC starts first setting the MSB (most significant bit, on an eight-bit ADC it would be D7). In order to facilitate the explanations below, consider an eight-bit ADC.

The comparison between Vin and the DAC output will tell the control unit if this bit should remain set at 1 or should be set at 0, as the op amp will tell right away the control unit if the sample value is greater or lower than 128 (2^7). Then D6 is set to one, and from the comparison done by the op amp, the control unit will know if this bit should remain set or not. And so on.

The good thing about the successive approximation ADC is its speed. At the worst case it will find the correct digital value for the sample at n clock cycles, where n is the number of bits used. For an eight-bit ADC, the digital value for each sample can be found in up to eight clock cycles (compare to 255 on the ramp counter), and for a 16-bit ADC the digital value for each sample can be found in up to 16 clock cycles (compare to 65,535 on the previous circuit).

And, as we mentioned, another great advantage of this circuit is the use of an output buffer, which allows the circuit that is fed by the ADC to read the digital data while the ADC is already working on the next sample.

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