Hardware Secrets

Home | Camera | Case | CE | Cooling | CPU | Input | Memory | Mobile | Motherboard | Networking | Power | Storage | Video | Other
First Look
Gabriel’s Blog
Main Menu
About Us
Awarded Products
Manufacturer Finder
On The Web
RSS Feed
Test Your Skills
Subscribe today!
Upgrading and Repairing PCs (21st Edition)
Upgrading and Repairing PCs (21st Edition), by Scott Mueller (Que Publishing), starting at $24.47

Home » CPU
Inside Intel Core Microarchitecture
Author: Gabriel Torres
Type: Tutorials Last Updated: April 12, 2006
Page: 7 of 7
Advanced Power Gating

With advanced power gating, Core microarchitecture brought CPU power saving to a totally new level. This feature enables the CPU to shut down units that aren’t being used at the moment. This idea goes even further, as the CPU can shut down specific parts inside each CPU unit in order to save energy, to dissipate less power and to provide a greater battery life (in the case of mobile CPUs).

Another power-saving capability of Core microarchitecture is to turn on only the necessary bits in the CPU internal busses. Many of the CPU internal busses are sized for the worst-case scenario – i.e., the largest x86 instruction that exists, which is a 15-byte wide instruction (480 bits)*. So, instead turning on all the 480 data lanes of this particular bus, the CPU can turn on only 32 of its data lanes, all that is necessary for transferring a 32-bit instruction, for example.

* You can find yourself quite lost by this statement, since you were always told that Intel architecture uses 32-bits instructions, so further explanation is necessary in order to clarify this affirmation.

Inside the CPU what is considered an instruction is the instruction opcode (the machine language equivalent of the assembly language instruction) plus all its required data. This is because in order to be executed, the instruction must enter the execution engine ”completed“, i.e., together with all its required data. Also, the size of each x86 instruction opcode is variable and not fixed at 32 bits, as you may think. For example, an instruction like mov eax, (32-bit data), which stores the (32-bit data) into the CPU’s EAX register is considered internally as a 40-bit length instruction (mov eax translates into a 8-bit opcode plus the 32 bits from its data). Actually, having instruction with several different lengths is what characterizes a CISC (Complex Instruction Set Computing) instruction set.

If you want to learn more about this subject, read AMD64 Architecture Programmer’s Manual Vol. 3: General Purpose and System Instructions (even though Intel provides the same information on their Intel Architecture Software Developer’s Manual Vol. 2A, AMD explanation and diagrams are easier to understand).

« Previous |  Page 7 of 7
Print Version | Send to Friend | Bookmark Article | Comments (0)

Related Content
  • IDF Fall 2005 Coverage
  • IDF Tel Aviv 2005 Coverage
  • All Pentium 4 Models
  • Core 2 Duo E6700 and Core 2 Extreme X6800 Review
  • All Core 2 Models

  • RSSLatest News
    LUXA2 Releases New P1-PRO Battery Power Pack
    October 1, 2013 - 7:23 AM PST
    MSI unveils GP70 and GP60 Laptops
    September 30, 2013 - 7:23 AM PST
    AMD Unveils Next-Generation Radeon Graphics Cards
    September 27, 2013 - 5:33 AM PST
    Genius Introduces Energy Mouse in North America
    September 27, 2013 - 5:32 AM PST
    Apple Updates iMac
    September 25, 2013 - 5:27 AM PST
    .:: More News ::.

    2004-13, Hardware Secrets, LLC. All rights reserved.
    Advertising | Legal Information | Privacy Policy
    All times are Pacific Standard Time (PST, GMT -08:00)