Intel Developer Forum (IDF) Spring 2006 edition has just started in San Francisco, CA. Today several announcements were made, the most important one being the details of Intel’s next-generation microarchitecture, now called Core, which will be used on Intel’s forthcoming processors. In this article you will see the highlights of the opening keynote given by Justin Rattner, Intel’s CTO, with the latest announcements by Intel on the CPU arena.

Rattner talked about his concern with power consumption and presented a very interesting chart showing energy per instruction vs. performance of several Intel CPUs, i.e. how much energy a given instruction consumes to be processed and the driven performance. As you can see on the chart, on Figure 1, this ratio was increasing rapidly until Pentium 4, but dropped to the same level of the very first Pentium processor with Pentium M. That is why Pentium M was the architecture of choice when Intel decided to replace Netburst architecture (which is used by Pentium 4). This ratio got even better with the introduction of Duo Core CPU (a.k.a. Yonah).

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Figure 1: Energy per instruction vs. performance.

Intel’s CTO also bragged about being one year ahead of competition in delivering 65 nm CPUs in volume to the market and showed us some interesting figures. Intel’s 65-nm process provides 20% greater performance and consumes 30% less energy than Intel’s 90-nm process. Intel’s 45-nm process will reach the market next year and will provide 20% performance increase and a 30% power reduction compared to 65 nm process.

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Figure 2: Intel’s 65-nm process advantages over 90-nm process.

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Figure 3: Intel’s 45-nm process advantages over 65-nm process.

With that, Ratter introduced Intel’s new microarchitecture, Core.