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The Unabridged Pentium 4: IA32 Processor Genealogy
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Home » CPU
Inside Pentium M Architecture
Author: Gabriel Torres
Type: Tutorials Last Updated: January 4, 2006
Page: 5 of 7
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Intel Pentium G620 Dual Core 2.6 GHz HD Graphics Retail LGA 1155 Processor BX80623G620 S735858220149 Electronics
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Reorder Buffer

So far the x86 instructions and the micro-ops resulted from them are transferred between the CPU stages in the same order they appear on the program being run.

Arriving at the ROB, micro-ops can be loaded and executed out-of-order by the execution units. After being executed, the instructions are sent back to the Reorder Buffer. Then at the Retirement stage, executed micro-ops are pulled out of the Reorder Buffer at the same order they entered it, i.e., they are removed in order. In Figure 4 you can have a better idea on how this works.

Pentium M Reorder Buffer
click to enlarge
Figure 4: How the Reorder Buffer works.

In Figure 4 we simplified the Reservation Station and the execution units for a better understanding of the Reorder Buffer. We will talk about these two stages in depth in the next page.

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