| Inside Pentium M Architecture |
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Real-time pricing for Intel BX80571E6500 |
| Intel Pentium Dual-Core Processor - 2.93GHz 2MB Cache 1066MHz FSB Wolfdale Dual Core Retail Socket 775 E6500 BX80571E6500 BX80571E6500 |
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| Reorder Buffer |
So far the x86 instructions and the micro-ops resulted from them are transferred between the CPU stages in the same order they appear on the program being run.
Arriving at the ROB, micro-ops can be loaded and executed out-of-order by the execution units. After being executed, the instructions are sent back to the Reorder Buffer. Then at the Retirement stage, executed micro-ops are pulled out of the Reorder Buffer at the same order they entered it, i.e. they are removed in order. On Figure 4 you can have a better idea on how this works.
click to enlarge
Figure 4: How the Reorder Buffer works.
On Figure 4 we simplified the Reservation Station and the execution units for a better understanding of the Reorder Buffer. We will talk about these two stages in depth on next page. |
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