| Intel EM64T Technology Explained |
|
|
| $ Check REAL-TIME pricing for Intel Core 2 Duo Retail Boxed E7200 Processor - 2.53GHz, 3MB Cache, 1066MHz FSB, 45nm Wolfdale E700 Boxed Processor $ |
|
|
|
|
|
|
|
| 64-Bit Mode Features |
Under IA32E 64-bit mode, the CPU gains a lot of new stuff:
- 64-bit addressing space, i.e. applications can address up to 16 EB (exabytes) of RAM (2^64 bytes); however externally current Celeron D, Pentium 4 and Xeon CPUs supporting EM64T have only 36 address lines, meaning they can “only” access 64 GB of RAM (2^36). Xeon DP CPUs supporting EM64T technology have 40 address lines, meaning they can access up to 1 TB (terabyte) of RAM (2^40). These limitations can be changed in the future, so in the future Intel can release CPUs that can access more RAM memory externally (up to 16 EB).
- Eight additional registers: under 64-bit mode the CPU has a total of 16 64-bit registers. These new registers are named R8 thru R15. Interesting enough, Intel has decided to use the same naming convention created by AMD on their 64-bit implementation, i.e. using a letter “R” to indicate a 64-bit register. On Figure 1 you can see how the 64-bit RAX register looks like.
 click to enlarge Figure 1: Register scheme on EM64T.
- Eight additional registers for SIMD instructions (MMX, SSE, SSE2, SSE3): the CPU has a total of 16 64-bit MMX registers under 64-bit mode. The XMM registers continue to be 128-bit wide, however the number of XMM registers were doubled from eight to 16. These registers are used by SSE floating point operations.
- All registers and instruction pointers are 64-bit wide. FPU registers continue to be 80-bit wide.
- All 64-bit registers continue to use the same division scheme that allows them to be used for 8-bit operations (see Figure 1). For example, the eight-bit AL register is, in fact, the eight least significant bits from RAX register. This scheme is called “uniform byte-register addressing”.
- Fast interrupt-priorization mechanism.
- A new 64-bit instruction pointer, called RIP, that replaces the 32-bit instruction pointer, called EIP.
- A new instruction pointer relative addressing mode, called RIP-relative addressing.
|
| Pages (3): « 1 [2] 3 » |
| Print Version | Send to Friend |
|
Bookmark Article
| Comments (0)
|
|
| Recommended Deals |  | AMD Athlon 64 3500+, 2.2 GHz (ada3500dik4b) OEM / Unboxed Processor
|  | AMD Athlon™ XP 2800+, 2.8 GHz (AXDA2800BOX) Retail Processor
|  | AMD Athlon™ 64 3800 3800+, 2 GHz AMD Processor in a Box (PIB)
|  | AMD Athlon™ 64 3000+, 2.0 GHz (ada3000box) AMD Processor in a Box (PIB)
|  | Intel Core™2 Quad Q6600, 2.40 GHz (BX80562Q6600) Boxed Processor
|
|
Latest News |
September 5, 2008 - 7:28 AM PST |
September 4, 2008 - 10:59 AM PST |
September 3, 2008 - 7:54 AM PST |
September 2, 2008 - 7:55 AM PST |
September 1, 2008 - 11:16 AM PST |
September 1, 2008 - 10:24 AM PST |
August 29, 2008 - 9:24 AM PST |
August 28, 2008 - 11:43 AM PST |
August 28, 2008 - 11:13 AM PST |
August 28, 2008 - 10:39 AM PST |
| .:: More News ::. |
|
Latest Content |
|
|
| Our Most Popular Articles |
772,156 views
|
480,318 views
|
425,639 views
|
413,859 views
|
408,621 views
|
385,116 views
|
347,758 views
|
333,076 views
|
280,116 views
|
270,314 views
|
|
| Latest Threads in Our Forums |
by tomahawk 1705 |
by BedCommando |
by jedsky |
by Wall'E |
by Gabriel Torres |
by Gabriel Torres |
by Hardware Secrets Team |
by andybarrel |
by Hardware Secrets Team |
by Retratserif |
| .:: Visit Our Forums ::. |
|
|