Each memory chip is organized internally as a matrix. At the intersection of each row and column we have a small capacitor that is in charge of storing a “0” or a “1” – the data. Inside the memory, the process of accessing the stored data is accomplished by first activating the row then the column where it is located. This activation is done by two control signals called RAS (Row Address Strobe) and CAS (Column Address Strobe). The less time there is between these two signals the better, as the data will be read sooner. RAS to CAS Delay or tRCD measures this time. In Figure 5 we illustrate this, showing a memory with tRCD = 3.

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Figure 5: RAS to CAS Delay (tRCD)

As you can see, RAS to CAS Delay is also the number of clock cycles taken between the “Active” command and a “read” or “write” command.

As with CAS Latency, RAS to CAS Delay works with the memory real clock (which is half of the labeled clock). The lower this parameter, the faster the memory will be, as it will start reading or writing data earlier.