What the allocator does:

• Reserves one of the 126 reorder buffers (ROB) to the current microinstruction, in order to keep track of the microinstruction completion status. This allows the microinstructions to be executed out-of-order, since the CPU will be able to put them in order again by using this table.
• Reserves on of the 128 register files (RF) in order to store there the data resulted from the microinstruction processing.
• If the microinstruction is a load or a store, i.e., it will read (load) or write (store) data from/to RAM memory, it will reserve one of the 48 load buffers or one of the 24 store buffers according.
• Reserves an entry on the memory or general queue, depending on the kind of microinstruction it is.

After that the microinstruction goes to the register renaming stage. CISC x86 architecture has only eight 32-bit registers (EAX, EBX, ECX, EDX, EBP, ESI, EDI and ESP). This number is simply too low, especially because modern CPUs can execute code out-of-order, what would ”kill“ the contents of a given register, crashing the program.

So, at this stage, the processor changes the name and contents of the registers used by the program into one of the 128 internal registers available, allowing the instruction to run at the same time of another instruction that uses the exact same standard register, or even out-of-order, i.e., this allows the second instruction to run before the first instruction even if they mess with the same register.
 
It is interesting to note that Pentium 4 has actually 256 internal registers, 128 registers for integer instructions and 128 registers for floating point and SSE instructions.

Pentium 4 renamer is capable of processing three microinstructions per clock cycle.

From the renamer the microinstructions go to a queue, according to its type: memory queue, for memory-related microinstructions, or Integer/Floating Point Queue, for all other instruction types.

click to enlarge
Figure 4: Allocator and Register Renamer.