In Figure 6, you can see a basic block diagram for a modern CPU. There are many differences between AMD and Intel architectures. Read or tutorial Inside Pentium 4 Architecture for a detailed view on Pentium 4 architecture. We still plan to write a specific tutorial about Athlon 64 architecture in the near future. We think that understanding the basic block diagram of a modern CPU is the first step to understand how CPUs from Intel and AMD work and the differences between them.

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Figure 6: Basic block diagram of a CPU.

The dotted line in Figure 6 represents the CPU body, as the RAM memory is located outside the CPU. The datapath between the RAM memory and the CPU is usually 64-bit wide (or 128-bit when dual channel memory configuration is used), running at the memory clock or the CPU external clock, which one is lower. The number of bits used and the clock rate can be combined in a unit called transfer rate, measured in MB/s. To calculate the transfer rate, the formula is number of bits x clock / 8. For a system using DDR400 memories in single channel configuration (64 bits) the memory transfer rate will be 3,200 MB/s, while the same system using dual channel memories (128 bits) will have a 6,400 MB/s memory transfer rate. For more information on this subject, read our tutorial Everything You Need to Know About DDR Dual Channel.

All the circuits inside the dotted box run at the CPU internal clock. Depending on the CPU some of its internal parts can even run at a higher clock rate. Also, the datapath between the CPU units can be wider, i.e., transfer more bits per clock cycle than 64 or 128. For example, the datapath between the L2 memory cache and the L1 instruction cache on modern processors is usually 256-bit wide. The higher the number the bits transferred per clock cycle, the fast the transfer will be done (in other words, the transfer rate will be higher). In Figure 5 we used a red arrow between the RAM memory and the L2 memory cache and green arrows between all other blocks to express the different clock rates and datapath width used.