When the bridge concept started to be used, the communication between the north bridge and the south bridge was done thru this bus, as we show on Figure 5. The problem of this approach is that the bandwidth available for the PCI bus – 132 MB/s – will be shared between all PCI devices in the system and devices hooked to the south bridge – especially hard disk drives. At that time, this wasn’t a problem, since hard drives maximum transfer rates were of 8 MB/s and 16 MB/s.

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Figure 5: Communication between north and south bridges using the PCI bus.

But when high-end video cards (at that time, the video cards were PCI) and high-performance hard disk drives were launched, a bottleneck situation arouse. Just think of modern ATA/133 hard disk drives, which have the same theoretical maximum transfer rate as the PCI bus! So, in theory, an ATA/133 hard drive would “kill” and the entire bandwidth, slowing down the communication speed of all devices connected to the PCI bus.

For the high-end video cards, the solution was the creation of a new bus connected directly to the north bridge, called AGP (Accelerated Graphics Port).

The final solution came when the chipset manufacturers started using a new approach: using a dedicated high-speed bus between north and south bridges and connecting the PCI bus devices to the south bridge.

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Figure 6: Communication between north and south bridges using a dedicated bus.

When Intel started using this architecture it started calling the bridges as “hubs”, the north bridge became MCH (Memory Controller Hub) and the south bridge became ICH (I/O Controller Hub). It is just a matter of nomenclature in order to clarify the architecture that is being used.

Using this new architecture, which is the architecture that motherboards use nowadays, when the CPU reads data from a hard drive, the data is transferred from the hard drive to the south bridge, then to the north bridge (using the dedicated bus) and then to the CPU (or directly to memory, if the Bus Mastering – a.k.a. DMA – method is being used). As you can see, the PCI bus is not used at all on this transfer, what didn’t happen on the previous architecture, since the PCI bus was in the middle of the road.

The speed of this dedicated bus depends on the chipset model. For example, on Intel 925X chipset this bus has a maximum transfer speed of 2 GB/s. Also, the manufacturers call this bus with different names:

• Intel: DMI (Direct Media Interface) or Intel Hub Architecture (*)
• ULi/ALi: HyperTransport
• VIA: V-Link
• SiS: MuTIOL (**)
• ATI: A-Link or PCI Express
• nVidia: HyperTransport (**)

(*) DMI interface is newer, used on i915 and i925 chipsets on and uses two separated data paths, one for data transmission and another for reception (full-duplex communication). Intel Hub Architecture, used by previous chipsets, uses the same data path for both transmission and reception (half-duplex communication).

(**) Some nVidia and SiS chipsets use only one chip, i.e. i.e. the functionalities of both north and south bridges are integrated into a single chip.

Also, on Radeon Xpress 200 from ATI, the communication between north and south bridges uses two PCI Express lanes. This doesn’t affect the performance of the system, because contrary to PCI, PCI Express bus is not shared between all PCI Express devices. It is a point-to-point solution, which means that the bus only connect two devices, the receiver and the transmitter; no other device can be attached to this connection. One lane is used for data transmission and the other for data reception (full-duplex communication).

HyperTransport bus also uses separated data paths, one for data transmission and another for reception (full-duplex communication). Click here to learn more about this bus.

If you want to know the details of a given chipset, just go to the chipset manufacturer website. Here you can find a complete list of chipset manufacturers and their websites.

As a last comment, you may be wondering what is “on-board PCI devices” listed on Figures 5 and 6. On-board devices like LAN and audio can be controlled by the chipset (south bridge) or by an extra controller chip. When this second approach is used, this controller chip is connected to the PCI bus.