Besides adding new clock rates – and thus new transfer rates – HyperTransport 3.0 brings several new features over HyperTransport 2.0, like AC operating mode, Link Splitting (a.k.a. Un-Ganging), Hot Plugging and Dynamic Link Clock/Width Adjustment. Forthcoming AMD processors, like Phenom, will use this new version of the HyperTransport bus.

HyperTransport 3.0 will be used on CPUs based on sockets AM2+ and 1207+.

HyperTransport 3.0 adds the following new clock rates, keeping compatibility with HT1 and HT2 rates (transfer rates assuming 16-bit links, which is the configuration used by AMD processors):

• 1,800 MHz = 3,600 MT/s = 7,200 MB/s
• 2,000 MHz = 4,000 MT/s = 8,000 MB/s
• 2,400 MHz = 4,800 MT/s = 9,600 MB/s
• 2,600 MHz = 5,200 MT/s = 10,400 MB/s

AMD is saying that their forthcoming CPUs will support the maximum HT3 transfer rate – 10,400 MB/s, which AMD calls 5.2 GT/s, i.e. billions of transfers per second. Keep in mind, however that these CPUs will still be compatible with lower rates. This means two things. First, new HT3-based CPUs can be installed on HT2-based motherboards – i.e. to install a socket AM2+ processor on a socket AM2 motherboard –, even though they won’t achieve their maximum I/O performance. The second thing is that at the time of launch maybe some chipsets won’t be able to run at 10,400 MB/s transfer rate, even if they are HT3, similarly to what happened when Athlon 64 was first launched.

Just like what happens with lower clock rates, probably there will be people calling HT3’s maximum clock rate as 5,2 GHz or its maximum transfer rate as 20,8 GB/s.

Once again the transfer rates announced by the HyperTransport consortium are highly exaggerated. They announce HyperTransport 3.0 as having a maximum transfer rate of 41.6 GB/s. To reach this number they considered 32-bit links (and not 16-bit links) and doubled the number found by two because there are two links available. The math used was 2,600 MHz x 32 x 2 / 8 x 2 links. As we have already explained, AMD processors use 16-bit links, not 32-bit ones, and we don’t agree with the methodology of doubling the transfer rate only because there is one link for transmitting and another for receiving data. We would only agree with this if the links were on the same direction.

Let’s now talk about the extra features brought by HyperTransport 3.0.

The new AC operating mode (translation: using a signaling system similar to networks) allows HyperTransport bus to achieve longer distances. The goal is to allow HyperTransport to be used directly to interconnect cases, boards and backplanes. Processors won’t use this feature.

Link splitting, also called un-ganging, allows the 16-bit link to be accessed as two independent 8-bit links. This can be used for increasing the number of links available, allowing more CPUs to be interconnected without using any extra fancy hardware.

Hot Plugging allows HyperTransport devices to be installed and removed with the bus running. It won’t allow you to replace your CPU with the system turned on because the CPU has several other pins besides the HyperTransport, but this feature may be used on storage servers based on HT3.

And finally Dynamic Link Clock/Width Adjustment, which will be used by HT3-based AMD CPUs – as long as they are installed on a motherboard using a HT3 chipset, of course. This feature allows the CPU to change the clock and the number of bits that are transmitted per clock cycle dynamically, i.e. “on the fly”. The idea here is to reduce power consumption. For example, if the CPU senses that running its HyperTransport bus at 2,600 MHz (10,400 MB/s) is too much for what it is doing right now, it can reduce the bus to 1,000 MHz (4,000 MB/s) – or whatever rate it thinks will be more suitable. The same goes for the number of bits transferred per clock cycle – it can be reduced from 16 to whatever number the CPU feels like, based on the current system usage.