HyperTransport 2.0 adds new clock rates – and thus new transfer rates – and a new feature, PCI Express mapping, which helps interfacing between HyperTransport and PCI Express – in order words, make it easier for the CPU to “talk” to PCI Express devices.

The new clock and transfer rates introduces by HyperTransport 2.0 are the following, assuming 16-bit links (which is the configuration used by AMD processors):

• 1,000 MHz = 2,000 MT/s = 4,000 MB/s
• 1,200 MHz = 2,400 MT/s = 4,800 MB/s
• 1,400 MHz = 2,800 MT/s = 5,600 MB/s

HyperTransport 2.0 devices can also work with HyperTransport 1.x transfer rates.

AMD uses HyperTransport 2.0 on all AMD64 CPUs based on sockets 939 and AM2 (except on Sempron CPUs, which continue to use HyperTransport 1.0), however supporting only the lower HT2 speed – in fact AMD was more interested in the PCI Express mapping feature than a higher transfer speed. So, even though these processors are based on HT2 the maximum transfer rate of their HT links are of 4,000 MB/s.

To make things a little bit confusing, AMD uses several times the name “HT1” to describe the HyperTransport bus of CPUs that have their HyperTransport links working at 1,000 MHz. This is probably to avoid people assuming that since they are HT2 parts they can work up to 1,400 MHz (5,600 MB/s), which is not the case, as we are explaining.

Also some people refer to this 1,000 MHz/4,000 MB/s HyperTransport link used by socket 939 and AM2 processors as:

• 2,000 MHz. This happens because since on each clock cycle two data are transferred, the performance obtained is similar to 2,000 MHz clock rate transferring only one data per clock cycle. At the end the transfer rate will be the same, as on the formula presented on the previous page instead of using “2” for “number of data per clock cycle”, it will be used “1” instead. This is the same thing that happens with DDR and later memories, where the announced clock rate is double the actual clock rate (e.g. DDR2-800 memories work in fact at 400 MHz transferring two data per clock cycle).
• 2,000 MT/s. This is the “official” AMD transfer rate. MT/s stands for Mega Transfers per Second, or millions of transfers per second. This is the correct way to express the above idea. Transfers per second are equal to the clock rate times the number of data transferred per clock cycle.
• 8,000 MB/s. This happens because the announced transfer rate is for each datapath (i.e. 4,000 MB/s for the input datapath and 4,000 MB/s for the output datapath), so some people simple multiply the transfer rate by two to cover the two datapaths. We don’t agree with this methodology. In brief, it is as if we said that a highway has a speed limit of 130 MPH just because there is a speed limit of 65 MPH in each direction. Makes no sense.

Another misunderstanding is saying that the external bus or FSB (Front Side Bus) of Athlon 64 (or any other AMD64-based CPU) is of 2,000 MHz. This is partially right. We can say this regarding I/O operations but not for memory, as processors based on AMD64 architecture have two separated external busses, as we saw. Thus it is better if you say HyperTransport and not “external bus” nor “FSB” to not create confusion.

Just like HyperTransport 1.x it is important to have in mind that socket 939 and AM2 processors can work with any of the clock rates below 1,000 MHz.

Once again official values for HyperTransport 2.0 are inflated as HyperTransport consortium announces them using 32-bit links and multiply them by two because there are two links available (one for transmitting and another for receiving data). As we mentioned before, we do not agree with this methodology. Because of this methodology HT2 maximum theoretical transfer rate is advertised as 22.4 GB/s (1,400 MHz x 32 x 2 / 8 x 2 links).