HyperTransport 2.0 (“HT2”) adds new clock rates (and thus new transfer rates) along with a new feature, PCI Express mapping, which makes it easier for the CPU to “talk” to PCI Express devices.

The new clock and transfer rates introduced by HyperTransport 2.0 are the following, assuming 16-bit links (which is the configuration used by AMD processors):

• 1,000 MHz = 2,000 MT/s = 4,000 MB/s
• 1,200 MHz = 2,400 MT/s = 4,800 MB/s
• 1,400 MHz = 2,800 MT/s = 5,600 MB/s

HyperTransport 2.0 devices can also work with HyperTransport 1.x transfer rates.

AMD uses HyperTransport 2.0 on all CPUs based on sockets 939 and AM2 (except on Sempron CPUs, which continue to use HyperTransport 1.0), however, supporting only the lower HT2 speed. In fact, AMD was more interested in the PCI Express mapping feature than a higher transfer speed. So even though these processors are based on HT2, the maximum transfer rate of their HT links is 4,000 MB/s.

To make things a little confusing, several times AMD uses the name “HT1” to describe the HyperTransport bus of CPUs that have their HyperTransport links working at 1,000 MHz. This is probably done to avoid people assuming that, since they are HT2 parts, they can work up to 1,400 MHz (5,600 MB/s), which is not the case, as we are explaining.

Also, some people refer to this 1,000 MHz (4,000 MB/s) HyperTransport link as:

• 2,000 MHz. This happens because since on each clock cycle two data are transferred, the performance obtained is similar to 2,000 MHz clock rate transferring only one data per clock cycle. In the end, the transfer rate will be the same, as in the formula presented in the previous page. Instead of using “2” for “number of data per clock cycle,” it will be using “1” instead.
• 2,000 MT/s. This is the “official” AMD transfer rate. MT/s stands for Mega Transfers per second, or Millions of Transfers per second. This is the correct way to express the above idea. Transfers per second are equal to the clock rate times the number of data transferred per clock cycle.
• 8,000 MB/s. This occurs because the announced transfer rate is for each datapath (i.e., 4,000 MB/s for the input datapath and 4,000 MB/s for the output datapath), so some people simply multiply the transfer rate by two to cover the two datapaths. As already discussed, we don’t agree with this methodology.

Another misunderstanding is saying that the external bus or FSB (Front Side Bus) of an AMD processor based on HT2 is 2,000 MHz. This is partially right. We can say this regarding I/O operations but not for memory, as processors based on AMD64 architecture have two separated external busses, as we saw. So it is better if you say “HyperTransport” or “HT,” rather than “external bus” or “FSB.”

As with the HyperTransport 1.x, it is important to keep in mind that AMD processors based on HyperTransport 2.0 can work with any of the clock rates below 1,000 MHz.

Once again, official values for the HyperTransport 2.0 are inflated, as HyperTransport consortium announces their using 32-bit links and multiplying the transfer rates by two, since there are two links available (one for transmitting and another for receiving data). As we previously mentioned, we do not agree with this methodology. Because of this methodology, the HT2 maximum theoretical transfer rate is advertised as 22.4 GB/s (1,400 MHz x 32 x 2 / 8 x 2 links).