Dynamic memories store data inside an array of tiny capacitors. DDR memories transfer two bits of data per clock cycle from the memory array to the memory internal I/O buffer. This is called 2-bit prefetch. On DDR2 this internal datapath was increased to four bits, and on DDR3 it was raised again to eight bits. This is actually the trick that allows DDR3 to work at higher clock rates than DDR2, and DDR2 at higher clock rates than DDR.

The clocks to which we have been referring so far are the clock rates on the “external world,” i.e., on the I/O interface from the memory, where the communication between the memory and the memory controller takes place. Internally, however, the memory works a little differently.

To better understand this idea, let’s compare a DDR-400, a DDR2-400 and a DDR3-400 memory chip. (We know that DDR3-400 memories don’t exist, but pretend they do.) These three chips work externally at 200 MHz transferring two data per clock cycle, achieving an external performance as if they were working at 400 MHz. Internally, however, the DDR chip transfers two bits between the memory array and the I/O buffer, so to match the I/O interface speed this datapath has to work at 200 MHz (200 MHz x 2 = 400 MHz). Since on DDR2 this datapath was increased from two bits to four bits, it can work at half the clock rate in order to achieve the same performance (100 MHz x 4 = 400 MHz). The same thing happens with DDR3. The datapath was doubled again to eight bits, so it can work at half the clock rate as DDR2 or only ¼ of the clock rate of DDR in order to achieve the same performance (50 MHz x 8 = 400 MHz).

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Figure 5: Understanding n-bit prefetching

Doubling the internal datapath at each generation means that each new memory generation can predictably have chip models with double the maximum clock rate achieved on the previous one. For example, on DDR-400, DDR2-800 and DDR3-1600 memories the memory works internally at the same clock rate (200 MHz).