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Everything You Need to Know About the Dual-, Triple-, and Quad-Channel Memory Architectures
 Author: Gabriel Torres 867,822 views Type: Tutorials Last Updated: November 2, 2011 Page: 2 of 9 Select Page to Load Introduction Bandwidth Dual-Channel Architecture Enabling Dual Channel Enabling Dual Channel (Intel and AMD Socket AM3+) Enabling Dual Channel (Other AMD Sockets) Triple-Channel Architecture Quad-Channel Architecture Checking if it is Correctly Enabled
Bandwidth
 Bandwidth is the maximum theoretical transfer rate of a communications channel. In the case of memories, the bandwidth is measured in megabytes per second (MB/s) or gigabytes per second (GB/s), meaning how many millions or billions of bytes can be transferred per second, respectively. One byte is a group of eight binary digits or bits, i.e., a sequence of eight 0’s or 1’s. The memory bandwidth can be determined through the following formula:bandwidth = real clock rate x data transferred per clock cycle x bits transferred per clock cycle / 8Memories based on the DDR (Double Data Rate) technology, such as DDR-SDRAM, DDR2-SDRAM, and DDR3-SDRAM, transfer two data per clock cycle. As a result, they achieve double the transfer rate compared to traditional memory technologies (such as the original SDRAM) running at the same clock rate. Because of that, DDR-based memories are usually labeled with double their real clock rate. For example, DDR3-1333 memories actually work at 666.6 MHz transferring two data per clock cycle, and thus are labeled as being a “1,333 MHz” device, even though the clock signal doesn’t really work at 1,333 MHz. You will need to use the real clock rate on the above formula, or you can simplify the formula as follows and use the DDR clock rate:bandwidth = DDR clock rate x bits transferred per clock cycle / 8Memory modules currently used are 64-bit devices. This means that 64 bits of data are transferred at each transfer cycle. Therefore, we will be using “64” as “bits transferred per clock cycle” in the above formula. Thus, we can simplify the bandwidth formula even further:bandwidth = DDR clock rate x 8That said, we can easily calculate the bandwidth of any memory. For example, DDR3-1333 memories have a bandwidth of 10,664 MB/s or 10.6 GB/s, and DDR3-1866 memories have a bandwidth of 14,928 MB/s or 14.9 GB/s.It is very important to understand that these transfer rates are the available bandwidth, i.e., the maximum theoretical transfer rates. When we calculate them, we are assuming that a data transfer will occur at each clock cycle (i.e., on a DDR3-1333 memory, 1.3 billion transfers per second will occur), which in fact never happens, because the CPU isn’t transferring data 100% of the time. That is why when you measure the actual memory transfer from your system using a program such as Sandra, you always get a value lower than the maximum theoretical transfer rate.The dual-, triple-, and quad-channel architectures work by increasing the number of data wires available in the memory bus, doubling, tripling or quadrupling the available bandwidth, respectively.It is very important to notice that this performance increase is achieved only on the memory subsystem; doubling the theoretical memory performance does not translate into a computer that is twice as fast. Only a small percentage of this memory performance increase will be reflected on the overall system performance.Let’s now examine exactly how each of those architectures work and how to enable them. Print Version | Send to Friend | Bookmark Article « Previous |  Page 2 of 9  | Next »

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