Introduction: AMD x86-64 Architecture
We will talk about the 64-bit processors that will drive our next personal computers forward. The projects by Intel and AMD are innovative and, if the promises are kept, in less than a year they should be on store shelves. These new architectures promise to take parallelism even farther, providing mechanisms for the compilers to pass to the CPUs not only efficiently organized instructions, but mainly how and which can be executed in parallel.
When we talk about 64-bit CPUs, it is important to elucidate a certain confusion that is made with present processors. We should have it clear in our minds that all the present processors, Intel or AMD, are 32-bit CPUs. The Pentium 4 or the Athlon have 64-bit data bus, but the CPU architecture is of 32 bits. In this article, we will see what the AMD is planning for its 64-bit architecture.
AMD x86-64 Architecture
We start with a question: how to make the transition from the 32-bit CPUs to the 64-bit one? AMD is answering this question with an architecture that, besides the 64-bit environment, promises compatibility with al the programs developed to 16 and 32 bits. The aim is to offer a low cost solution for the users to make this transition in a very easy way. With an architecture compatible to the x86 world, the board and software manufacturers and the users can manage their investments more easily. The idea is to offer a secure bridge for the transition from 32 to 64 bits. The 64 -computing is directed to applications that are very hungry for memory, such as the great databases, the CAD tools and the simulations that, according to the present features, are limited by the 4 GB address space.
Very little time ago, people used to say that the RISC CPUs would definitely go beyond the CISC architectures. However, it did not happen and the present CISC computers got on the same footing with the RISC, in terms of integer data operations, and have already reduced a lot the disadvantage they had in operations with floating point. That is why, states AMD, the next performance gains will have more to do with the implementing techniques (e.g.: parallelism) than with the instruction set: RISC, CISC-64 or VLIW. In fact, there is a certain abuse with these names, because the present x86 CPUs have only one CISC external layer, and its core was formed by RISC computers.
AMD is calling its new architecture x86-64 and it will be started with a family of processors that have the code name Hammer (the first project, code-named clawhammer, was released as Athlon 64). The 64-bit strategy by AMD is the extension of the present x86 CPUs to work at 64 bits, with the introduction of the so called Long Mode. This solution is safe because it has already been employed at the time of the transition from 16 bits (8088 and 286 CPUs) to 32 bits (386 CPUs and forward). Since long ago, the 32-bit CPUs operate in two modes. When in real mode, they become like the old 8088, but, when in protected mode, they offer 32-bit features, with task and memory managers. The x86-64 architecture offers a new mode called Long Mode, which serves for setting the CPU to operate at 64 bits. When in long mode, besides the 64-bit features, registers extended to 64 bits are offered and, besides that, new registers have been added. Let’s go to the study of this new mode.