Convington (Celeron SEPP)

The first Celeron processor to be launched was an economic version of Pentium II Deschutes core. It had 32KB of L1 cache, no L2 cache, MMX technology, worked externally with 66 MHz, and was found in a printed circuit board called SEPP (Single Edge Processor Package), which was connected to the slot 1 motherboard, and was available at speeds of 266 MHz and 300 MHz.

The motherboard used by this Celeron version was the same used by the Pentium II and first Pentium III processors.

All Celeron Models

Figure 1: Celeron processor with SEPP package.

Main features of Celeron SEPP were:

  • Based on Pentium II with Deschutes core
  • Manufacturing process: 0.25 μm
  • L1 cache: 32 KB total, 16 KB for instructions and 16 KB for data
  • L2 cache: not available (0 KB)
  • External clock rate: 66 MHz
  • Packaging: SEPP
  • Socket: Slot 1

Available models of SEPP Celeron are listed on the chart below. TDP stands for Thermal Design Power and indicates the CPU maximum thermal dissipation.

Model Internal Clock Voltage TDP 
SL2YN  266 MHz 2 V 16.59 W
SL2QG  266 MHz 2 V 16.59 W
SL2SY  266 MHz 2 V 16.59 W
SL2TR  266 MHz 2 V 16.59 W
SL2X8  300 MHz 2 V 18.48 W
SL2Y2  300 MHz 2 V 18.48 W
SL27Z  300 MHz 2 V 18.48 W
SL2YP  300 MHz 2 V 18.48 W
SL2Z7  300 MHz 2 V 18.48 W